Datasheet

 1998-2013 Microchip Technology Inc. DS30605D-page 129
PIC16C63A/65B/73B/74B
FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Note: Refer to Figure 16-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param No. Sym Characteristic Min Typ† Max Units Conditions
62*
TdtV2wrH Data in valid before WR or CS (setup time) 20 — — ns
63*
TwrH2dtI
WR
 or CS to data in
invalid (hold time)
PIC16CXX
20 — — ns
PIC16LCXX
35 — — ns
64
TrdL2dtV
RD
 and CS to data out valid
——80ns
65*
TrdH2dtI
RD
 or CS to data out invalid
10 — 30 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.