Datasheet

PIC16C63A/65B/73B/74B
DS30605D-page 128  1998-2013 Microchip Technology Inc.
FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 16-4 for load conditions.
CCPx
(Capture mode)
50 51
52
CCPx
53
54
(Compare or PWM mode)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
50* TccL CCP1 and
CCP2
input low time
No Prescaler 0.5T
CY + 20 — — ns
With Prescaler PIC16CXX 10 — — ns
PIC16LCXX 20 — — ns
51* TccH CCP1 and
CCP2
input high time
No Prescaler 0.5T
CY + 20 — — ns
With Prescaler PIC16CXX 10 — — ns
PIC16LCXX 20 — — ns
52* TccP CCP1 and CCP2 input period 3T
CY + 40
N
— — ns N = prescale
value (1,4, or 16)
53* TccR CCP1 and CCP2 output rise time PIC16CXX — 10 25 ns
PIC16LCXX — 25 45 ns
54* TccF CCP1 and CCP2 output fall time PIC16CXX — 10 25 ns
PIC16LCXX — 25 45 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.