Datasheet

 1997-2013 Microchip Technology Inc. DS30234E-page 61
PIC16C6X
5.7 Parallel Slave Port
PORTD operates as an 8-bit wide parallel slave port
(microprocessor port) when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through
R
D control input (RE0/RD) and WR control input pin
(RE1/WR
).
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD
to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data flow.
A write to the PSP occurs when both the CS
and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input Buf-
fer Full status flag bit IBF (TRISE<7>) is set on the Q4
clock cycle, following the next Q2 cycle, to signal the
write is complete (Figure 5-12). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The input Buffer Overflow status flag bit
IBOV (TRISE<5>) is set if a second write to the Parallel
Slave Port is attempted when the previous byte has not
been read out of the buffer.
A read from the PSP occurs when both the CS
and RD
lines are first detected low. The Output Buffer Full sta-
tus flag bit OBF (TRISE<6>) is cleared immediately
(Figure 5-13) indicating that the PORTD latch is waiting
to be read by the external bus. When either the CS
or
RD
pin becomes high (level triggered), the interrupt flag
bit PSPIF is set on the Q4 clock cycle, following the next
Q2 cycle, indicating that the read is complete. OBF
remains low until data is written to PORTD by the user
firmware.
When not in Parallel Slave Port mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previ-
ously set, it must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
Applicable Devices
61 62 62A R62 63 R636464AR646565AR6566 67
FIGURE 5-11: PORTD AND PORTE AS A
PARALLEL SLAVE PORT
Data bus
WR
PORT
RD
RDx
QD
CK
EN
QD
EN
PORT
pin
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL