Datasheet

PIC16C6X
DS30234E-page 304  1997-2013 Microchip Technology Inc.
APPENDIX C: WHAT’S NEW
Added PIC16CR63 and PIC16CR65 devices.
Added PIC16C66 and PIC16C67 devices. The
PIC16C66/67 devices have 368 bytes of data memory
distributed in 4 banks and 8K of program memory in 4
pages. These two devices have an enhanced SPI that
supports both clock phase and polarity. The USART
has been enhanced.
When upgrading to the PIC16C66/67 please note that
the upper 16 bytes of data memory in banks 1,2, and 3
are mapped into bank 0. This may require relocation of
data memory usage in the user application code.
Q-cycles for instruction execution were added to Sec-
tion 14.0 Instruction Set Summary.
APPENDIX D: WHAT’S CHANGED
Minor changes, spelling and grammatical changes.
Divided SPI section into SPI for the PIC16C66/67
(Section 11.3) and SPI for all other devices
(Section 11.2).
Added the following note for the USART. This applies to
all devices except the PIC16C66 and PIC16C67.
For the PIC16C63/R63/65/65A/R65 the asynchronous
high speed mode (BRGH = 1) may experience a high
rate of receive errors. It is recommended that BRGH =
0. If you desire a higher baud rate than BRGH = 0 can
support, refer to the device errata for additional infor-
mation or use the PIC16C66/67.
APPENDIX E: REVISION E
January 2013 - Added a note to each package drawing.