Datasheet

PIC16C6X
DS30234E-page 96  1997-2013 Microchip Technology Inc.
11.4.2 ADDRESSING I
2
C DEVICES
There are two address formats. The simplest is the
7-bit address format with a R/W
bit (Figure 11-15). The
more complex is the 10-bit address with a R/W
bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.
FIGURE 11-15: 7-BIT ADDRESS FORMAT
FIGURE 11-16: I
2
C 10-BIT ADDRESS FORMAT
11.4.3 TRANSFER ACKNOWLEDGE
All data must be transmitted per byte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK
) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).
S
R/W
ACK
Sent by
Slave
slave address
S
R/W
Read/Write pulse
MSb LSb
Start Condition
ACK
Acknowledge
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
S
R/W
ACK
- Start Condition
- Read/Write Pulse
- Acknowledge
FIGURE 11-17: SLAVE-RECEIVER
ACKNOWLEDGE
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 11-18. The slave will inherently stretch the
clock, when it is a transmitter, but will not when it is a
receiver. The slave will have to clear the SSPCON<4>
bit to enable clock stretching when it is a receiver.
S
Data
Output by
Tra ns mit t e r
Data
Output by
Receiver
SCL from
Master
Start
Condition
Clock Pulse for
Acknowledgment
not acknowledge
acknowledge
1
2
8
9
FIGURE 11-18: DATA TRANSFER WAIT STATE
12 78 9 123  89
P
SDA
SCL
S
Start
Condition
Address R/W
ACK Wait
State
Data ACK
MSB acknowledgment
signal from receiver
acknowledgment
signal from receiver
byte complete
interrupt with receiver
clock line held low while
interrupts are serviced
Stop
Condition
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67