PIC16C63A/65B/73B/74B 8-Bit CMOS Microcontrollers with A/D Converter • PIC16C63A • PIC16C73B • PIC16C65B • PIC16C74B PIC16CXX Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • 4 K x 14 words of Program Memory, 192 x 8 bytes of Data Memory (RAM) • Interrupt capability • Eight-level deep hardware stac
PIC16C63A/65B/73B/74B SDIP, SOIC, Windowed CERDIP 3 26 4 25 5 6 7 8 9 10 21 20 19 17 13 16 14 15 RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC 18 12 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 39 38 37 36 35 34 33 32 31 30 29 PIC16C65B PIC16C74B 22 Key Features PIC® Mid-Range MCU Family Reference Manual (DS33023) 1 2 3 4 5 6 7 8 9 10 11 PIC16C65B PIC16C74B 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS
PIC16C63A/65B/73B/74B Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C63A/65B/73B/74B Device Varieties ................................................................................................................................. 7 3.0 Architectural Overview ..............................................................................
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 4 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 1.0 GENERAL DESCRIPTION The PIC16C63A/65B/73B/74B devices are low cost, high performance, CMOS, fully-static, 8-bit microcontrollers in the PIC16CXX mid-range family. All PIC® microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack and multiple internal and external interrupt sources.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 6 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 2.0 PIC16C63A/65B/73B/74B DEVICE 2.3 VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C63A/65B/73B/74B Product Identification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 8 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture, in which program and data are fetched from the same memory using the same bus.
PIC16C63A/65B/73B/74B FIGURE 3-1: PIC16C63A/65B/73B/74B BLOCK DIAGRAM 13 8 Data Bus Program Counter PORTA RA0/AN0(2) RA1/AN1(2) RA2/AN2(2) RA3/AN3/VREF(2) RA4/T0CKI RA5/SS/AN4(2) EPROM Program Memory Program Bus RAM File Registers 8 Level Stack (13-bit) 14 RAM Addr(1) PORTB 9 Addr MUX Instruction reg Direct Addr 7 RB0/INT Indirect Addr 8 RB7:RB1 FSR reg STATUS reg PORTC 8 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brown-
PIC16C63A/65B/73B/74B TABLE 3-1: PIC16C63A/73B PINOUT DESCRIPTION Pin Name DIP Pin# SOIC Pin# I/O/P Type Buffer Type Description ST/CMOS(3) Oscillator crystal input/external clock source input. OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PIC16C63A/65B/73B/74B TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION TQFP I/O/P MQFP Type Pin# DIP Pin# PLCC Pin# OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input. This pin is an active low RESET to the device.
PIC16C63A/65B/73B/74B TABLE 3-2: PIC16C65B/74B PINOUT DESCRIPTION (CONTINUED) TQFP I/O/P MQFP Type Pin# Pin Name DIP Pin# PLCC Pin# RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output.
PIC16C63A/65B/73B/74B 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC16C63A/65B/73B/74B 4.0 MEMORY ORGANIZATION 4.2 4.1 Program Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 are the bank select bits. The PIC16C63A/65B/73B/74B has a 13-bit program counter capable of addressing an 8K x 14 program memory space. All devices covered by this data sheet have 4K x 14 bits of program memory. The address range is 0000h - 0FFFh for all devices.
PIC16C63A/65B/73B/74B FIGURE 4-2: REGISTER FILE MAP File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(2) PORTE(2) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES(3) ADCON0(3) INDF(1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD(2) TRISE(2) PCLATH INTCON P
PIC16C63A/65B/73B/74B TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(3) Bank 0 INDF(4) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h PCL(4) Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000 00h 03h STATUS 04h FSR(4) 05h PORTA 06h POR
PIC16C63A/65B/73B/74B TABLE 4-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS(3) Bank 1 80h INDF(4) 81h OPTION_REG 82h PCL(4) 83h STATUS(4) 84h FSR(4) 85h TRISA 86h TRISB PORTB Data Direction register 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 88h TRISD(5) PORTD Data Direction register 1111 1111 1111 1111 89h TRISE(5) IBF OBF IBOV 8Ah PCLATH(1,
PIC16C63A/65B/73B/74B 4.2.2.1 STATUS Register The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16C63A/65B/73B/74B 4.2.2.2 OPTION Register Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the watchdog timer.
PIC16C63A/65B/73B/74B 4.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts. REGISTER 4-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>).
PIC16C63A/65B/73B/74B 4.2.2.4 PIE1 Register Note: This register contains the individual enable bits for the peripheral interrupts. REGISTER 4-4: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16C63A/65B/73B/74B 4.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the peripheral interrupts. REGISTER 4-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16C63A/65B/73B/74B 4.2.2.6 PIE2 Register This register contains the individual enable bit for the CCP2 peripheral interrupt. REGISTER 4-6: PIE2 REGISTER (ADDRESS 8Dh) U-0 — bit 7 U-0 — U-0 — bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt U-0 — U-0 — U-0 — U-0 — R/W-0 CCP2IE bit 0 Legend: 4.2.2.
PIC16C63A/65B/73B/74B 4.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 4-8: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16C63A/65B/73B/74B 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 4-3 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16C63A/65B/73B/74B 4.5 EXAMPLE 4-2: Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. movlw movwf clrf incf btfss goto NEXT Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 28 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 5.0 I/O PORTS FIGURE 5-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Registers Data Bus BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS D Q VDD WR Port Q CK P Data Latch PORTA is a 6-bit latch. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output.
PIC16C63A/65B/73B/74B TABLE 5-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0(1) bit0 TTL Digital input/output or analog input. RA1/AN1(1) bit1 TTL Digital input/output or analog input. bit2 TTL Digital input/output or analog input. bit3 TTL Digital input/output or analog input or VREF. RA4/T0CKI bit4 ST Digital input/output or external clock input for Timer0. Output is open drain type.
PIC16C63A/65B/73B/74B 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>).
PIC16C63A/65B/73B/74B TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT bit0 TTL/ST(1) Function RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up.
PIC16C63A/65B/73B/74B 5.3 FIGURE 5-5: PORTC and TRISC Registers PORTC is an 8-bit bi-directional port. Each pin is individually configurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers. PORTC BLOCK DIAGRAM PORT/PERIPHERAL Select(2) Peripheral Data Out Data Bus WR Port When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin.
PIC16C63A/65B/73B/74B 5.4 FIGURE 5-6: PORTD and TRISD Registers Note: Data Bus The PIC16C63A and PIC16C73B do not provide PORTD. The PORTD and TRISD registers are not implemented. PORTD BLOCK DIAGRAM D Q I/O pin(1) WR Port CK PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. Data Latch D WR TRIS PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>).
PIC16C63A/65B/73B/74B 5.5 FIGURE 5-7: PORTE and TRISE Register Note 1: The PIC16C63A and PIC16C73B do not provide PORTE. The PORTE and TRISE registers are not implemented. Data Bus WR Port 2: The PIC16C63A/65B does not provide an A/D module. A/D functions are not implemented. PORTE has three pins: RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configured as inputs or outputs. These pins have Schmitt Trigger input buffers.
PIC16C63A/65B/73B/74B REGISTER 5-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Mic
PIC16C63A/65B/73B/74B 5.6 Note: Parallel Slave Port (PSP) The PIC16C63A and PIC16C73B do not provide a parallel slave port. The PORTD, PORTE, TRISD and TRISE registers are not implemented. PORTD operates as an 8-bit wide Parallel Slave Port (PSP), or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world, through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR/AN6.
PIC16C63A/65B/73B/74B FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 5-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name 08h PORTD 09h PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port data latch when written, Port pins when read Value on: POR, BOR
PIC16C63A/65B/73B/74B 6.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment, either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.
PIC16C63A/65B/73B/74B 6.2 Using Timer0 with an External Clock module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 6-1). The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the synchronized input on the Q2 and Q4 cycles of the internal phase clocks.
PIC16C63A/65B/73B/74B TABLE 6-1: Address REGISTERS ASSOCIATED WITH TIMER0 Name Bit 7 Bit 6 01h TMR0 0Bh,8Bh INTCON 81h OPTION_REG RBPU INTEDG Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module’s register GIE PEIE Value on: POR, BOR Value on all other RESETS xxxx xxxx uuuu uuuu T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 42 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 7.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16C63A/65B/73B/74B 7.1 Timer1 Operation in Timer Mode 7.2 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS.
PIC16C63A/65B/73B/74B 7.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.1).
PIC16C63A/65B/73B/74B TABLE 7-2: Address Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for
PIC16C63A/65B/73B/74B 8.0 TIMER2 MODULE 8.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2.
PIC16C63A/65B/73B/74B TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF (1) Value on all other RESETS 0000 000x 0000 000u (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Ch PIR1 PSPIF ADIF 8Ch PIE1 PSPIE(1) ADIE(2) 11h TMR2 12h T2CON 92h PR2 0000 0000 0000 00
PIC16C63A/65B/73B/74B 9.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 9-1 and Table 9-2 show the resources and interactions of the CCP module(s).
PIC16C63A/65B/73B/74B REGISTER 9-1: CCP1CON REGISTER/CCP2CON REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16C63A/65B/73B/74B 9.1 9.1.2 Capture Mode TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following and is configured using CCPxCON<3:0>: Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. • • • • 9.1.
PIC16C63A/65B/73B/74B 9.2 9.2.4 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set. SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action.
PIC16C63A/65B/73B/74B A PWM output (Figure 9-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 9-4: PWM OUTPUT Period 9.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs.
PIC16C63A/65B/73B/74B TABLE 9-4: Address 0Bh,8Bh 0Ch REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Name INTCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE PSPIF PIR1 (1) T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 ADIF 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2
PIC16C63A/65B/73B/74B 10.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE 10.1 SSP Module Overview FIGURE 10-1: Internal Data Bus Read The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16C63A/65B/73B/74B REGISTER 10-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Select (see F
PIC16C63A/65B/73B/74B REGISTER 10-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Flag bit 1 = The SSPBUF register was written while still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Synchronous Serial Port Overflow Flag bit In SPI mode: 1 = A new byte was received while the SSPBUF register is stil
PIC16C63A/65B/73B/74B FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF DS30605D-page 58 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit6 bit7 bit5 bit3 bit4 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 10-1: Address 0Bh,8Bh 0Ch REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE T0IF INTF RBIF PIR1 PSPIF (1) (1) ADIF Value on: POR, BOR Value on all other RESETS T0IE INTE RBIE (2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 000
PIC16C63A/65B/73B/74B 10.3 SSP I 2C Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementation of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer, the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA).
PIC16C63A/65B/73B/74B 10.3.1.1 Addressing 1. Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16C63A/65B/73B/74B 10.3.1.2 Reception a) When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. b) When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as any situation where a received byte in SSPBUF is overwritten by the next received byte before it has been read.
PIC16C63A/65B/73B/74B 10.3.1.3 Transmission An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
PIC16C63A/65B/73B/74B 10.3.2 MASTER MODE 10.3.3 Master mode of operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear.
PIC16C63A/65B/73B/74B 11.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC16C63A/65B/73B/74B REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care
PIC16C63A/65B/73B/74B 11.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16C63A/65B/73B/74B 11.2 USART Asynchronous Mode This interrupt can be enabled/disabled by setting/clearing the USART Transmit Enable bit TXIE (PIE1<4>). The flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register.
PIC16C63A/65B/73B/74B Steps to follow when setting up an Asynchronous Transmission: 4. 1. 5. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 11.1) Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set interrupt enable bits TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE (INTCON<7>), as required. 2. 3. FIGURE 11-2: If 9-bit transmission is desired, then set transmit bit TX9.
PIC16C63A/65B/73B/74B 11.2.2 USART ASYNCHRONOUS RECEIVER ered register, i.e., it is a two-deep FIFO. It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO.
PIC16C63A/65B/73B/74B Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 11.1). Enable the asynchronous serial port by clearing bit SYNC, and setting bit SPEN. If interrupts are desired, set interrupt enable bits RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE (INTCON<7>), as required. If 9-bit reception is desired, then set bit RX9.
PIC16C63A/65B/73B/74B 11.2.3 USART SYNCHRONOUS MASTER MODE In Synchronous Master mode, the data is transmitted in a half-duplex manner, i.e., transmission and reception do not occur at the same time. When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16C63A/65B/73B/74B TABLE 11-5: Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x RCIE TXIE SSPIE CCP1IE TXEN SYNC — BRGH Address 0Bh,8Bh REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION (1) (2) 0Ch PIR1 18h RCSTA 19h TXREG US
PIC16C63A/65B/73B/74B 11.2.5 USART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence.
PIC16C63A/65B/73B/74B TABLE 11-6: Address 0Bh,8Bh REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u RCIF TXIF SSPIF CCP1IF TMR2IF SREN CREN — FERR OERR RCIE TXIE SSPIE CCP1IE TMR2IE TXEN SYNC — BRGH TRMT 0Ch PIR1 18h RCSTA PSPIF (1) SPEN ADIF (2) RX9 1Ah RCREG USART Receive register 8C
PIC16C63A/65B/73B/74B 11.3 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 11.3.
PIC16C63A/65B/73B/74B TABLE 11-7: Address 0Bh,8Bh REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION RBIF 0000 000x 0000 000u 0000 0000 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF PIR1 18h RCSTA 8Ch Value on all other RESETS Bit 7 0Ch 19h Value on: POR, BOR Name PSPIF TXREG (1) SPEN PSPIE 98h TXSTA 99h SPBRG RX9 RCIF TXIF SREN CREN SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 — FERR OERR RX9D 0000 -00x 0000 -00x 0000
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 78 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 12.0 Note: ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The PIC16C63A and PIC16C65B do not include A/D modules. ADCON0, ADCON1 and ADRES registers are not implemented. ADIF and ADIE bits are reserved and should be maintained clear. The 8-bit Analog-to-Digital (A/D) converter module has five inputs for the PIC16C73B and eight for the PIC16C74B. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number.
PIC16C63A/65B/73B/74B REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 000 001 010 011 100 101 11x A A A A A A D A A A A A A D A A A A D D D A A A A D D D A VREF A VREF A VREF D A = Analog input RE0(1) RE1(1) RE2(1) A A D D D D D A A D D D D D A A D D D D D VREF VDD RA3 VDD
PIC16C63A/65B/73B/74B The following steps should be followed for doing an A/D conversion: 1. 2. 3. 4. 5. Configure the A/D module: • Configure analog pins, voltage reference, and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit (PIR1<6>) • Set ADIE bit (PIE1<6>) • Set PEIE bit (INTCON<6>) • Set GIE bit (INTCON<7>) FIGURE 12-1: Wait the required acquisition time.
PIC16C63A/65B/73B/74B 12.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 12-2.
PIC16C63A/65B/73B/74B 12.2 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.5 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: • • • • 2 TOSC 8 TOSC 32 TOSC Internal RC oscillator (2 - 6 S) For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time (parameter #130). 12.
PIC16C63A/65B/73B/74B TABLE 12-1: Address 0Bh,8Bh SUMMARY OF A/D REGISTERS (PIC16C73B/74B ONLY) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u (1) 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP1IF --
PIC16C63A/65B/73B/74B 13.0 SPECIAL FEATURES OF THE CPU timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only and is designed to keep the part in RESET, while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry.
PIC16C63A/65B/73B/74B 13.2 13.2.1 Oscillator Configurations LP XT HS RC 13.2.2 CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) OSCILLATOR TYPES The PIC16CXX can be operated in four different oscillator modes.
PIC16C63A/65B/73B/74B TABLE 13-1: CERAMIC RESONATORS Ranges Tested: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 68 - 100 pF 15 - 68 pF 15 - 68 pF 68 - 100 pF 15 - 68 pF 15 - 68 pF HS 8.0 MHz 16.0 MHz 10 - 68 pF 10 - 22 pF 10 - 68 pF 10 - 22 pF Note: Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time.
PIC16C63A/65B/73B/74B 13.3 RESET The PIC16CXX differentiates between various kinds of RESET: • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) Brown-out Reset (BOR) A simplified block diagram of the on-chip RESET circuit is shown in Figure 13-4. Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in any other RESET.
PIC16C63A/65B/73B/74B 13.4 13.4.1 RESETS POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (parameters D003 and D004, in the range of 1.5V - 2.1V). To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a POR.
PIC16C63A/65B/73B/74B TABLE 13-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Oscillator Configuration Brown-out Wake-up from SLEEP 1024TOSC 72 ms + 1024TOSC 1024TOSC — 72 ms — PWRTE = 0 PWRTE = 1 XT, HS, LP 72 ms + 1024TOSC RC 72 ms TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCL
PIC16C63A/65B/73B/74B TABLE 13-6: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt W 63A 65B 73B 74B xxxx xxxx INDF 63A 65B 73B 74B N/A TMR0 63A 65B 73B 74B xxxx xxxx PCL 63A 65B 73B 74B 0000h 0000h PC + 1(2) STATUS 63A 65B 73B 74B 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTA 63A 65B 73B 74B --0x 0000 --0u
PIC16C63A/65B/73B/74B TABLE 13-6: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset Brown-out Reset MCLR Resets WDT Reset Wake-up via WDT or Interrupt ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISA 63A 65B 73B 74B --11 1111 --11 1111 --uu uuuu TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu T
PIC16C63A/65B/73B/74B 13.5 Interrupts The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts.
PIC16C63A/65B/73B/74B FIGURE 13-5: INTERRUPT LOGIC PSPIF PSPIE ADIF ADIE Wake-up (If in SLEEP mode) T0IF T0IE RCIF RCIE INTF INTE TXIF TXIE SSPIF SSPIE Interrupt to CPU RBIF RBIE PEIE CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts.
PIC16C63A/65B/73B/74B 13.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Users may wish to save key registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software. Example 13-1 stores and restores the STATUS, W, and PCLATH registers. The register W_TEMP must be defined in each bank and must be defined at the same offset from the bank base address (i.e.
PIC16C63A/65B/73B/74B 13.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst case conditions (VDD = Min., Temperature = Max., and max. WDT prescaler), it may take several seconds before a WDT time-out occurs. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
PIC16C63A/65B/73B/74B 13.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the WDT will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16C63A/65B/73B/74B FIGURE 13-7: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency GIE bit (INTCON<7>) (2) Processor in SLEEP INSTRUCTION FLOW PC PC Instruction Fetched Inst(PC) = SLEEP Instruction Executed Inst(PC - 1) Note 13.
PIC16C63A/65B/73B/74B 14.0 INSTRUCTION SET SUMMARY Each PIC16CXX instruction is a 14-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1 shows the opcode field descriptions.
PIC16C63A/65B/73B/74B TABLE 14-2: PIC16CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Mov
PIC16C63A/65B/73B/74B 14.1 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [label] ADDLW Syntax: [label] ANDWF Operands: 0 k 255 Operands: Operation: (W) + k (W) 0 f 127 d Status Affected: C, DC, Z Operation: (W) .AND. (f) (destination) The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register. Status Affected: Z Description: AND the W register with register 'f'.
PIC16C63A/65B/73B/74B BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [label] BTFSS f,b Syntax: [label] CLRF Operands: 0 f 127 0b<7 Operands: 0 f 127 Operation: Operation: skip if (f) = 1 00h (f) 1Z Status Affected: None Status Affected: Z Description: If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruction is discarded and a NOP is executed instead making this a 2TCY instruction.
PIC16C63A/65B/73B/74B COMF Complement f Syntax: [ label ] COMF GOTO Unconditional Branch Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: (f) (destination) Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f'. Description: GOTO is an unconditional branch.
PIC16C63A/65B/73B/74B IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: 0 k 255 Operation: (W) .OR. k (W) Operation: k (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register. Description: The eight bit literal 'k' is loaded into W register. The don’t cares will assemble as 0’s.
PIC16C63A/65B/73B/74B RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS PC, 1 GIE 0 f 127 d [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16C63A/65B/73B/74B SUBLW Subtract W from Literal XORLW Exclusive OR Literal with W Syntax: [ label ] SUBLW k Syntax: [label] Operands: 0 k 255 Operands: 0 k 255 Operation: k - (W) W) Operation: (W) .XOR. k W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC16C63A/65B/73B/74B 15.
PIC16C63A/65B/73B/74B 15.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16C63A/65B/73B/74B 15.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F87X and can be used to develop for this and other PIC microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the in-circuit debugging capability built into the PIC16F87X.
PIC16C63A/65B/73B/74B 15.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 1998-2013 Microchip Technology Inc. † † * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 112 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 16.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) ..........................................
PIC16C63A/65B/73B/74B FIGURE 16-1: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V 5.0 V PIC16CXXX-20 Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 20 MHz Frequency FIGURE 16-2: PIC16LC63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V 4.5 V PIC16LCXXX-04 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
PIC16C63A/65B/73B/74B FIGURE 16-3: PIC16C63A/65B/73B/74B VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC16CXXX-04 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz Frequency 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 16.1 DC Characteristics PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No. Sym Min Typ† Max Units PIC16LCXXX 2.5 VBOR* – – 5.5 5.5 V V LP, XT, RC osc modes (DC - 4 MHz) BOR enabled (Note 7) PIC16CXXX 4.0 4.5 VBOR* – – – 5.5 5.5 5.5 V V V XT, RC and LP osc mode HS osc mode BOR enabled (Note 7) – 1.5 – V – VSS – V D004* SVDD VDD Rise Rate to ensure internal D004A* Power-on Reset signal 0.05 TBD – – – – D005 3.65 – 4.
PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No. Sym IDD Characteristic D010A PIC16CXXX D010 D013 IPD Min Typ† Max Units Conditions – 0.6 2.0 mA – 22.5 48 A XT, RC osc modes: FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc mode: FOSC = 32 kHz, VDD = 3.0V, WDT disabled – 2.
PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No.
PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions 2.0 – VDD V 4.
PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature 0°C TA +70°C for commercial -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions – – 0.6 V IOL = 8.
PIC16C63A/65B/73B/74B PIC16LC63A/65B/73B/74B-04 ‡PIC16C63A/65B/73B/74B-04 ‡PIC16C6A/65B/73B/74B-20 Param No.
PIC16C63A/65B/73B/74B 16.2 16.2.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16C63A/65B/73B/74B 16.2.2 TIMING CONDITIONS The temperature and voltages specified in Table 16-1 apply to all timing specifications unless otherwise noted. Figure 16-4 specifies the load conditions for the timing specifications.
PIC16C63A/65B/73B/74B 16.2.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 16-5: EXTERNAL CLOCK TIMING Q1 Q4 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 16-2: Param No.
PIC16C63A/65B/73B/74B FIGURE 16-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) 20, 21 Refer to Figure 16-4 for load conditions. Note: TABLE 16-3: Param No.
PIC16C63A/65B/73B/74B FIGURE 16-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 16-4 for load conditions. FIGURE 16-8: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 16-4: Param No.
PIC16C63A/65B/73B/74B FIGURE 16-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 16-4 for load conditions. TABLE 16-5: Param No. Sym 40* Tt0H TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width Min No Prescaler With Prescaler 41* Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42* Tt0P T0CKI Period No Prescaler 0.
PIC16C63A/65B/73B/74B FIGURE 16-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture mode) 50 51 52 CCPx (Compare or PWM mode) 53 Note: Refer to Figure 16-4 for load conditions. TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Sym No.
PIC16C63A/65B/73B/74B FIGURE 16-11: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 16-4 for load conditions. TABLE 16-7: Param No.
PIC16C63A/65B/73B/74B FIGURE 16-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 16-4 for load conditions. TABLE 16-8: Param No. EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Symbol Characteristic Min 70 TssL2scH, TssL2scL SS to SCK or SCK input TCY — — ns 71 TscH SCK input high time (Slave mode) 1.
PIC16C63A/65B/73B/74B FIGURE 16-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 16-4 for load conditions. TABLE 16-9: Param No. EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Symbol 71 71A TscH 72 TscL 72A 73 Characteristic Min Typ† Max Units SCK input high time (Slave mode) Continuous 1.
PIC16C63A/65B/73B/74B FIGURE 16-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 16-4 for load conditions. TABLE 16-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0) Param No.
PIC16C63A/65B/73B/74B FIGURE 16-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 16-4 for load conditions. TABLE 16-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic Min TssL2scH, TssL2scL SS to SCK or SCK input TCY — — ns TscH SCK input high time (Slave mode) TscL SCK input low time (Slave mode) 1.
PIC16C63A/65B/73B/74B I2C BUS START/STOP BITS TIMING FIGURE 16-16: SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 16-4 for load conditions. TABLE 16-12: I2C BUS START/STOP BITS REQUIREMENTS Param No.
PIC16C63A/65B/73B/74B TABLE 16-13: I2C BUS DATA REQUIREMENTS Param. No. Sym 100* THIGH Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC16C63A/65B/73B/74B FIGURE 16-18: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 16-4 for load conditions. TABLE 16-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16C63A/65B/73B/74B TABLE 16-16: A/D CONVERTER CHARACTERISTICS: PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL) Param Sym No.
PIC16C63A/65B/73B/74B FIGURE 16-20: A/D CONVERSION TIMING BSF ADCON0, GO 134 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 7 A/D DATA 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 16-17: A/D CONVERSION REQUIREMENTS Param Sym No.
PIC16C63A/65B/73B/74B 17.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some graphs or tables the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B FIGURE 17-1: TYPICAL IDD vs. FOSC OVER VDD – HS MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 7 6 IDD (mA) 5 4 5.5 V 5.0 V 3 4.5 V 4.0 V 2 3.5 V 3.0 V 1 2.5 V 0 4 6 8 10 12 14 16 18 20 FOSC (MHz) FIGURE 17-2: MAXIMUM IDD vs. FOSC OVER VDD – HS MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 7 6 5 IDD (mA) 5.5 V 4 5.0 V 4.5 V 3 4.
PIC16C63A/65B/73B/74B FIGURE 17-3: TYPICAL IDD vs. FOSC OVER VDD – LP MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 100 90 5.5 V 80 70 5.0 V IDD (µA) 60 4.5 V 50 4.0 V 40 3.5 V 30 3.0 V 20 2.5 V 10 0 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 17-4: MAXIMUM IDD vs. FOSC OVER VDD – LP MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 160 140 5.
PIC16C63A/65B/73B/74B FIGURE 17-5: TYPICAL IDD vs. FOSC OVER VDD – XT MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.4 1.2 5.5 V 1.0 IDD (mA) 5.0 V 0.8 4.5 V 0.6 4.0 V 3.5 V 0.4 3.0 V 2.5 V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 17-6: MAXIMUM IDD vs. FOSC OVER VDD – XT MODE Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.8 1.6 5.5 V 1.
PIC16C63A/65B/73B/74B FIGURE 17-7: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 20 PF Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.5 Not recommended for operation over 4 MHz 4.0 3.3 k 3.5 FOSC (MHz) 3.0 5.1 k 2.5 2.0 1.5 10 k 1.0 0.5 100 k 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-8: AVERAGE FOSC vs.
PIC16C63A/65B/73B/74B FIGURE 17-9: AVERAGE FOSC vs. VDD FOR VARIOUS RESISTANCES – RC MODE; C = 300 PF Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1,000 900 800 700 FOSC (kHz) 3.3 k 600 500 5.1 k 400 300 10 k 200 100 100 k 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-10: VTH vs. VDD OVER TEMPERATURE – TTL INPUT Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.8 1.
PIC16C63A/65B/73B/74B FIGURE 17-11: VIL, VIH vs. VDD OVER TEMPERATURE – SCHMITT TRIGGER INPUT (I2C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 4.0 3.5 VIH Typ (25°C) VIH Max (125°C) 3.0 VIH Min (-40°C) VIN (V) 2.5 2.0 VIL Max (125°C) 1.5 VIL Typ (25°C) VIL Min (-40°C) 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-12: VIL, VIH vs.
PIC16C63A/65B/73B/74B FIGURE 17-13: VOH vs. IOH AT VDD = 3.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 3.5 3.0 2.5 VOH (V) Max (-40°C) 2.0 Typical (25°C) 1.5 1.0 Min (125°C) 0.5 0.0 0 5 10 15 20 25 IOH (mA) FIGURE 17-14: VOH vs. IOH AT VDD = 5.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 5.5 5.0 4.5 Max (-40°C) 4.0 Typical (25°C) VOH (V) 3.5 3.0 2.
PIC16C63A/65B/73B/74B FIGURE 17-15: VOL vs. IOL AT VDD = 3.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.4 2.2 2.0 1.8 1.6 Max (125°C) VOL (V) 1.4 1.2 1.0 Typ (25°C) 0.8 0.6 0.4 Min (-40°C) 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 IOL (-mA) FIGURE 17-16: VOL vs. IOL AT VDD = 5.0 V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 1.8 1.6 1.4 VOL (V) 1.
PIC16C63A/65B/73B/74B FIGURE 17-17: IPD vs. VDD (85°C) – SLEEP MODE, ALL PERIPHERALS DISABLED Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 140 Max 85°C 120 IPD (nA) 100 80 60 Typ 85°C 40 20 Max 25°CMax -40°C 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-18: IPD vs.
PIC16C63A/65B/73B/74B FIGURE 17-19: IBOR vs. VDD OVER TEMPERATURE (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 200 180 160 140 IBOR (uA) Max (125°C) 120 100 Typ (25°C) Device in RESET 80 60 Indeterminant State Device in SLEEP Max (125°C) Typ (25°C) RESET current depends on oscillator mode, frequency, and circuit. 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-20: ITIMER1 vs.
PIC16C63A/65B/73B/74B FIGURE 17-21: IWDT vs. VDD (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 20 18 16 IWDT (µA) 14 12 Max (-40°C to 125°C) 10 8 Typical (25°C) 6 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 17-22: WDT PERIOD vs.
PIC16C63A/65B/73B/74B FIGURE 17-23: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 40 35 WDT Period (ms) 30 125°C 25 85°C 20 25°C 15 -40°C 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 152 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B 18.0 PACKAGING INFORMATION 18.1 Package Marking Information 28-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead CERDIP Windowed Example PIC16C73B-04/SP 0017HAT Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC 0017CAT Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC16C73B-20/SO 0017SAA Example 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC16C63A/65B/73B/74B Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 40-Lead CERDIP Windowed PIC16C74B-04/P 0017SAA Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead MQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30605D-page 154 PIC16C74B/JW 0017HAT Example PIC16C74B -20/PT 0017HAT Example PIC16C7
PIC16C63A/65B/73B/74B 18.2 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 2.54 .100 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.
PIC16C63A/65B/73B/74B 18.3 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D W2 2 n 1 W1 E A2 A c L Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C63A/65B/73B/74B 18.4 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C63A/65B/73B/74B 18.5 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C63A/65B/73B/74B 18.6 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 1 n E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC16C63A/65B/73B/74B 18.7 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 2 1 n E A2 L c B1 B eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C63A/65B/73B/74B 18.8 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C63A/65B/73B/74B 18.9 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form (MQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C63A/65B/73B/74B 18.10 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B c E2 Units Dimension Limits n p A1 p D2 INCHES* NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 164 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B APPENDIX A: REVISION HISTORY Version Date Revision Description A 7/98 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234, and the PIC16C7X Data Sheet, DS30390. B 1/99 Corrections to Version A data sheet for technical accuracy. Added data: • Operation of the SMP and CKE bits of the SSPSTAT register in I2C mode have been specified • Frequency vs.
PIC16C63A/65B/73B/74B APPENDIX C: DEVICE MIGRATIONS PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B This document is intended to describe the functional differences and the electrical specification differences that are present when migrating from one device to the next. Table C-1 shows functional differences, while Table C-2 shows electrical and timing differences.
PIC16C63A/65B/73B/74B TABLE C-2: Param No. SPECIFICATION DIFFERENCES PIC16C63/65A/73A/74A Symbol PIC16C63A/65B/73B/74B Characteristic Unit Min Typ† Max 4.0 — — — 6.0 — Brown-out Reset Voltage Open-Drain High Voltage on RA4 3.7 — 4.0 — 4.3 14.0 Reference voltage Conversion time (Note 2) (not including S/H time) 3.0 — Min Typ† Max 4.0 — — 5.5 5.5 V V — — 4.35 8.
PIC16C63A/65B/73B/74B APPENDIX D: MIGRATION FROM BASELINE TO MID-RANGE DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16CXXX). The following are the list of modifications over the PIC16C5X microcontroller family: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14-bits.
PIC16C63A/65B/73B/74B INDEX A A/D ADCON0 Register....................................................... 79 ADCON1 Register....................................................... 80 Analog Input Model Block Diagram............................. 82 Analog-to-Digital Converter......................................... 79 Block Diagram............................................................. 81 Configuring Analog Port Pins...................................... 83 Configuring the Interrupt ...................
PIC16C63A/65B/73B/74B D D/A ...................................................................................... 56 Data Memory Register File Map ........................................................ 16 Data/Address bit, D/A.......................................................... 56 DC bit .................................................................................. 19 Development Support ........................................................... 5 Device Differences ...........................
PIC16C63A/65B/73B/74B O OERR bit ............................................................................. 66 OPCODE ............................................................................ 99 OPTION Register ................................................................ 20 OSC Selection .................................................................... 85 Oscillator HS ......................................................................... 86, 90 LP............................................
PIC16C63A/65B/73B/74B R R/W ..................................................................................... 56 R/W bit .................................................................... 61, 62, 63 RBIF bit ......................................................................... 31, 94 RBPU bit ............................................................................. 20 RC Oscillator ................................................................. 87, 90 RCSTA Register..........................
PIC16C63A/65B/73B/74B TMR1H ............................................................... 45 TMR1L ................................................................ 45 Timer2 Block Diagram .................................................... 47 Module ................................................................ 47 Postscaler ........................................................... 47 Prescaler............................................................. 47 T2CON......................................
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 174 1998-2013 Microchip Technology Inc.
THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X -XX Frequency Temperature Range Range /XX XXX Package Pattern Examples: a) b) Device PIC16C6X(1), PIC16C6XT(2); VDD range 4.0V to PIC16LC6X(1), PIC16LC6XT(2); VDD range 2.5V PIC16C7X(1), PIC16C7XT(2); VDD range 4.0V to PIC16LC7X(1), PIC16LC7XT(2); VDD range 2.5V Frequency Range 04 20 5.5V to 5.5V 5.5V to 5.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 178 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 180 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: DS30605D-page 182 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B NOTES: 1998-2013 Microchip Technology Inc.
PIC16C63A/65B/73B/74B DS30605D-page 184 1998-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
