Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 4 MHz I/O number 22

 2001 Microchip Technology Inc. DS80094A-page 1

PIC16C63

The PIC16C63 (Rev. A) parts you have received con-

form functionally to the Device Data Sheet

(DS30234D), except for the anomalies described

below.

All the problems listed here will be addressed in future

revisions of the PIC16C63 silicon.

1. Module: CCP (Compare Mode)

The Compare mode may not operate as expected

when configuring the compare match to drive the

I/O pin low (CCPxM<3:0> = 1001).

When the CCP module is changed to compare

output low (CCPxM<3:0> = 1001) from any other

non-compare CCP mode, the I/O pin will immedi-

ately be driven low, regardless of the state of the

I/O data latch. The pin will remain low when the

compare match occurs (see Table 1).

However, when the CCP module is changed to

compare output high (CCPxM<3:0> = 1000) from

any other CCP mode, the I/O pin will immediately

be driven low, regardless of the state of the I/O

data latch. The pin will be driven high when the

compare match occurs.

TABLE 1: COMPARE OUTPUT LOW

SWITCHING

Work around

To have the I/O pin high until the compare match

low occurs, force a compare match high to get the

I/O pin into the high state, then reconfigure the

compare match to force the I/O low when the com-

pare condition occurs.

2. Module: CCP (Compare Mode)

The special event trigger of the Compare mode

may not occur if both of the following conditions

exist:

• An instruction, one cycle (T

CY) prior to a

Timer1/Compare register match has literal

data equal to the address of a CCP register

being used. Specific cases include:

• An instruction in the same cycle as a

Timer1/Compare register match has an

MSb of ‘0’.

The interrupt for the compare event will still be

generated, but no special event trigger will occur.

Work around

Use the Interrupt Service Routine instead of using

the special event trigger to reset Timer1 (and start

an A/D conversion, if applicable).

3. Module: SSP Module (I

C™ mode)

If the bus is active when the I

C mode is enabled,

and the next 8-bits of data on the bus match the

address of the device, then the SSP module will

generate an Acknowledge pulse.

Work around

Before enabling the I

C mode, ensure that the bus

is not active.

CCP Mode

CCPxM<3:0> =

I/O pin

State

Change CCP to

CCPxM<3:0> =

1001 1000

0xxx

HLL

LLL

1000

HH—

LL—

1001

H — L

L — L

101x

HLL

LLL

11xx

HLL

LLL

Unit Register Literal Data

CCP1

CCPR1L 15h

CCPR1H 16h

CCP1CON 17h

CCP2

CCPR2L 1Bh

CCPR2H 1Ch

CCP2C0N 1Dh

PIC16C63 Rev. A Silicon Errata Sheet

Summary of content (8 pages)

PAGE 1
PIC16C63 PIC16C63 Rev. A Silicon Errata Sheet The PIC16C63 (Rev. A) parts you have received conform functionally to the Device Data Sheet (DS30234D), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC16C63 silicon. 1.
PAGE 2
PIC16C63 4. Module: SSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1). FIGURE 1: SCK PULSE VARIATION USING TIMER2/2 Write SSPBUF bit0=1 bit1=0 bit2=1 . . . . SD0 The Timer1 value may unexpectedly increment if either the TMR1H or the TMR1L register is written.
PAGE 3
PIC16C63 7. Module: USART When the USART (SCI) is configured in Asynchronous mode with the BRGH bit set, a high number of receive errors may be experienced. For asynchronous receive operations, it is recommended that the USART be configured with the BRGH bit cleared.  2001 Microchip Technology Inc.
PAGE 4
PIC16C63 Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS30234D), the following clarifications and corrections should be noted. 1. Module: I/O Ports The specification for the High Voltage Open Drain I/O (parameter D150, the RA4 pin) cannot be met without possible long term reliability issues on that I/O pin. If a high voltage drive is required, use an external transistor that can support the required voltage. The new value is shown in Table 1.
PAGE 5
PIC16C63 3. Module: Timer1 The operation of Timer1 needs some clarification when the timer registers are written when the TMR1ON bit is set. When the TMR1H and/or TMR1L registers are written while this clock is low, TMR1 will not increment on the next rising edge of this clock, but must first have a falling clock and the rising clock for TMR1 to increment. The internal clock signal that is the input to the TMR1 prescaler affects the incrementing of Timer1 (TMR1H:TMR1L registers and the Timer1 prescaler).
PAGE 6
PIC16C63 4. Module: RC Oscillator The table for RC Oscillator Frequencies in the Device Characterization section of the Data Sheet is incorrect. The correct characterization information is shown in Table 3. TABLE 3: RC OSCILLATOR FREQUENCIES CHARACTERIZATION CHANGES FROM DATA SHEET Correct Characterization Data Current Data Sheet Values REXT CEXT 22 pF 100 pF 330 pF Average % Variation Average % Variation 5.1 K 3.55 MHz ± 9.63% 4.12 MHz ± 1.4% 10 K 1.99 MHz ± 10.53% 2.35 MHz ± 1.
PAGE 7
“All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise.
PAGE 8
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