Datasheet

 2003 Microchip Technology Inc. DS30235J-page 59
PIC16C62X
9.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD
bit in the STATUS register is
cleared, the TO
bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before
SLEEP was executed (driving high, low, or hi-
impedance).
For lowest current consumption in this mode, all I/O
pins should be either at V
DD or VSS with no external
circuitry drawing current from the I/O pin and the
comparators and V
REF should be disabled. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at V
DD or
V
SS for lowest current consumption. The contribution
from on chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
9.8.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO
and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD
bit, which is set on power-up, is cleared when
SLEEP is invoked. TO
bit is cleared if WDT wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following
SLEEP is not desirable, the
user should have an
NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note: It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC PC+1 PC+2
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 1)
SLEEP
Processor in
SLEEP
Interrupt Latency
(Note 2)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2 0004h 0005h
Dummy cycle
Tos t(2)
PC+2
Note 1: XT, HS or LP Oscillator mode assumed.
2: T
OST = 1024TOSC (drawing not to scale) This delay will not be there for RC Osc mode.
3: GIE = '1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = '0',
execution will continue in-line.
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.