Datasheet

PIC16C62X
DS30235J-page 50  2003 Microchip Technology Inc.
9.4 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
9.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
V
DD has reached a high enough level for proper
operation. To take advantage of the POR, just tie the
MCLR
pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for V
DD is
required. See Electrical Specifications for details.
The POR circuit does not produce an internal RESET
when V
DD declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
9.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as PWRT
is active. The PWRT delay allows the V
DD to rise to an
acceptable level. A configuration bit, PWRTE
can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always
be enabled when Brown-out Reset is enabled.
The Power-up Time delay will vary from chip-to-chip
and due to V
DD, temperature and process variation.
See DC parameters for details.
9.4.3 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4 BROWN-OUT RESET (BOR)
The PIC16C62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Reset circuitry. If V
DD falls below 4.0V refer
to V
BOR parameter D005 (VBOR) for greater than
parameter (T
BOR) in Table 12-5. The brown-out situa-
tion will RESET the chip. A RESET won’t occur if V
DD
falls below 4.0V for less than parameter (TBOR).
On any RESET (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in RESET until V
DD rises above
BV
DD. The Power-up Timer will now be invoked and will
keep the chip in RESET an additional 72 ms.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
DD
rises above BVDD, the Power-Up Timer will execute a
72 ms RESET. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 9-7
shows typical Brown-out situations.
FIGURE 9-7: BROWN-OUT SITUATIONS
72 ms
BV
DD
VDD
INTERNAL
RESET
BVDD
VDD
INTERNAL
RESET
72 ms
<72 ms
72 ms
BV
DD
VDD
INTERNAL
RESET