Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SOIC 18 8-Bit 4 MHz I/O number 13

 2003 Microchip Technology Inc. DS30235J

PIC16C62X

Data Sheet

EPROM-Based 8-Bit

CMOS Microcontrollers

Summary of content (128 pages)

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PIC16C62X Data Sheet EPROM-Based 8-Bit CMOS Microcontrollers  2003 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC16C62X EPROM-Based 8-Bit CMOS Microcontrollers Devices included in this data sheet: Referred to collectively as PIC16C62X.
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PIC16C62X Device Differences Voltage Range Oscillator Process Technology (Microns) 2.5 - 6.0 See Note 1 0.9 PIC16C621 2.5 - 6.0 See Note 1 0.9 PIC16C622(3) 2.5 - 6.0 See Note 1 0.9 PIC16C620A(4) 2.7 - 5.5 See Note 1 0.7 PIC16CR620A(2) 2.5 - 5.5 See Note 1 0.7 2.7 - 5.5 See Note 1 0.7 Device PIC16C620(3) (3) PIC16C621A (4) PIC16C622A(4) 2.7 - 5.5 See Note 1 0.7 Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
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PIC16C62X Table of Contents 1.0 General Description .................................................................................................................................................................. 5 2.0 PIC16C62X Device Varieties .................................................................................................................................................... 7 3.0 Architectural Overview ......................................................................................
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PIC16C62X NOTES: DS30235J-page 4  2003 Microchip Technology Inc.
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PIC16C62X 1.0 GENERAL DESCRIPTION The PIC16C62X devices are 18 and 20-Pin ROM/ EPROM-based members of the versatile PICmicro® family of low cost, high performance, CMOS, fullystatic, 8-bit microcontrollers. All PICmicro microcontrollers employ an advanced RISC architecture. The PIC16C62X devices have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
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PIC16C62X TABLE 1-1: PIC16C62X FAMILY OF DEVICES PIC16C620(3) PIC16C620A(1)(4) PIC16CR620A(2) PIC16C621(3) PIC16C621A(1)(4) PIC16C622(3) PIC16C622A(1)(4) Clock Maximum Frequency 20 of Operation (MHz) 40 20 20 40 20 40 Memory EPROM Program Memory (x14 words) 512 512 1K 1K 2K 2K 512 Data Memory (bytes) 80 96 96 80 96 128 128 TMR0 TMR0 TMRO TMR0 TMR0 TMR0 TMR0 Comparators(s) 2 2 2 2 2 2 2 Internal Reference Voltage Yes Yes Yes Yes Yes Yes Yes Interrupt Sources
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PIC16C62X 2.0 PIC16C62X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C62X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.
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PIC16C62X NOTES: DS30235J-page 8  2003 Microchip Technology Inc.
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PIC16C62X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture, where program and data are fetched from the same memory.
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PIC16C62X FIGURE 3-1: BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC16C620 PIC16C620A PIC16CR620A PIC16C621 PIC16C621A PIC16C622 PIC16C622A 512 x 14 512 x 14 512 x 14 1K x 14 1K x 14 2K x 14 2K x 14 80 x 8 96 x 8 96 x 8 80 x 8 96 x 8 128 x 8 128 x 8 13 8 Data Bus Program Counter Voltage Reference EPROM Program Memory Program Bus RAM File Registers 8-Level Stack (13-bit) 14 RAM Addr (1) 9 Comparator RA0/AN0 Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg RA
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PIC16C62X TABLE 3-1: Name OSC1/CLKIN PIC16C62X PINOUT DESCRIPTION DIP/SOIC Pin # SSOP Pin # I/O/P Type Buffer Type 16 18 I ST/CMOS OSC2/CLKOUT MCLR/VPP Description Oscillator crystal input/external clock source input. 15 17 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.
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PIC16C62X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC16C62X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16C62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C620(A) and PIC16CR620, 1K x 14 (0000h 03FFh) for the PIC16C621(A) and 2K x 14 (0000h 07FFh) for the PIC16C622(A) are physically implemented.
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PIC16C62X 4.2 Data Memory Organization The data memory (Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7) is partitioned into two banks, which contain the General Purpose Registers and the Special Function Registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the first 32 locations of each bank.
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PIC16C62X FIGURE 4-4: DATA MEMORY MAP FOR THE PIC16C620/621 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 6Fh INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PIR1 PCLATH INTCON PIE1 PCON CMCON VRCON File Address File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
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PIC16C62X FIGURE 4-6: DATA MEMORY MAP FOR THE PIC16C620A/CR620A/621A File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PIR1 PCLATH INTCON PIE1 PCON CMCON VRCON File Address File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh
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PIC16C62X 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets (core and peripheral). The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. The Special Function Registers are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1).
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PIC16C62X 4.2.2.1 STATUS Register The STATUS register, shown in Register 4-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC16C62X 4.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1).
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PIC16C62X 4.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 and Section 4.2.2.5 for a description of the comparator enable and flag bits. REGISTER 4-3: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
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PIC16C62X 4.2.2.4 PIE1 Register This register contains the individual enable bit for the comparator interrupt. REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH) U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — CMIE — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as '0' bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt bit 5-0 Unimplemented: Read as '0' Legend: 4.2.2.
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PIC16C62X 4.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Reset. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is cleared, indicating a brown-out has occurred. The BOR STATUS bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the Configuration word).
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PIC16C62X 4.3 4.3.2 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any RESET, the PC is cleared. Figure 4-8 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC16C62X 4.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-1: movlw movwf NEXT clrf incf btfss goto The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h.
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PIC16C62X 5.0 I/O PORTS Note: The PIC16C62X have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Registers On RESET, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.
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PIC16C62X FIGURE 5-3: Data Bus BLOCK DIAGRAM OF RA3 PIN Comparator Mode = 110 D Q Comparator Output WR PORTA VDD Q CK Data Latch D VDD P Q RA3 Pin N WR TRISA CK Q VSS VSS TRIS Latch Analog Input Mode Schmitt Trigger Input Buffer RD TRISA Q D EN RD PORTA To Comparator FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4 PIN Comparator Mode = 110 D Q Comparator Output WR PORTA CK Q Data Latch D Q RA4 Pin N WR TRISA CK Q VSS VSS TRIS Latch Schmitt Trigger Input Buffer RD TRISA Q D EN
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PIC16C62X TABLE 5-1: PORTA FUNCTIONS Bit # Buffer Type RA0/AN0 bit0 ST Input/output or comparator input RA1/AN1 bit1 ST Input/output or comparator input RA2/AN2/VREF bit2 ST Input/output or comparator input or VREF output RA3/AN3 bit3 ST Input/output or comparator input/output bit4 ST Input/output or external clock input for TMR0 or comparator output. Output is open drain type.
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PIC16C62X 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a High Impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s). Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations.
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PIC16C62X TABLE 5-3: PORTB FUNCTIONS Name Bit # Buffer Type Function RB0/INT bit0 TTL/ST(1) Input/output or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change).
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PIC16C62X 5.3 I/O Programming Considerations 5.3.1 EXAMPLE 5-2: BI-DIRECTIONAL I/O PORTS READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
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PIC16C62X 6.0 TIMER0 MODULE The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.
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PIC16C62X FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6 MOVWF TMR0 MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W Instruction Fetch T0+1 T0 TMR0 Instruction Execute Write TMR0 executed FIGURE 6-4: NT0+1 NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 + 1 TI
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PIC16C62X 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
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PIC16C62X 6.3 Prescaler The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer.
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PIC16C62X 6.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the TMR0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to WDT.) EXAMPLE 6-1: 1.
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PIC16C62X NOTES: DS30235J-page 36  2003 Microchip Technology Inc.
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PIC16C62X 7.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The OnChip Voltage Reference (Section 8.0) can also be an input to the comparators. REGISTER 7-1: The CMCON register, shown in Register 7-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 7-1.
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PIC16C62X 7.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 7-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 7-1: RA0/AN0 RA3/AN3 RA1/AN1 RA2/AN2 mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 12-2.
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PIC16C62X The code example in Example 7-1 depicts the steps required to configure the comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators. EXAMPLE 7-1: INITIALIZING COMPARATOR MODULE MOVLW 0x03 ;Init comparator mode MOVWF CMCON ;CM<2:0> = 011 CLRF PORTA ;Init PORTA BSF STATUS,RP0 ;Select Bank1 MOVLW 0x07 ;Initialize data direction MOVWF TRISA ;Set RA<2:0> as inputs 7.
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PIC16C62X 7.4 Comparator Response Time 7.5 Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Table 12-2). Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read only.
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PIC16C62X 7.6 Comparator Interrupts wake up the device from SLEEP mode when enabled. While the comparator is powered-up, higher SLEEP currents than shown in the power-down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP.
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PIC16C62X TABLE 7-1: Address REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on All Other RESETS 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ----
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PIC16C62X 8.0 VOLTAGE REFERENCE MODULE 8.1 The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows: The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used.
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PIC16C62X EXAMPLE 8-1: MOVLW 8.4 VOLTAGE REFERENCE CONFIGURATION 0x02 Effects of a RESET A device RESET disables the voltage reference by clearing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The VREF value select bits, VRCON<3:0>, are also cleared. ; 4 Inputs Muxed MOVWF CMCON ; to 2 comps.
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PIC16C62X 9.0 SPECIAL FEATURES OF THE CPU Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. The PIC16C62X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8.
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PIC16C62X 9.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. These bits are mapped in program memory location 2007h. REGISTER 9-1: CP1 CP0 (2) The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/configuration memory space (2000h – 3FFFh), which can be accessed only during programming.
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PIC16C62X 9.2 Oscillator Configurations 9.2.1 OSCILLATOR TYPES LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 9.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 9-1). The PIC16C62X oscillator design requires the use of a parallel cut crystal.
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PIC16C62X 9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance or one with parallel resonance. Figure 9-3 shows implementation of a parallel resonant oscillator circuit.
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PIC16C62X 9.3 RESET The PIC16C62X differentiates between various kinds of RESET: a) b) c) d) e) f) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) WDT wake-up (SLEEP) Brown-out Reset (BOR) A simplified block diagram of the on-chip RESET circuit is shown in Figure 9-6. Some registers are not affected in any RESET condition Their status is unknown on POR and unchanged in any other RESET.
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PIC16C62X 9.4 9.4.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) The Power-up Time delay will vary from chip-to-chip and due to VDD, temperature and process variation. See DC parameters for details. 9.4.3 POWER-ON RESET (POR) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
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PIC16C62X 9.4.5 TIME-OUT SEQUENCE 9.4.6 On power-up the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in RC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 9-8, Figure 9-9 and Figure 9-10 depict time-out sequences. The power control/STATUS register, PCON (address 8Eh), has two bits. Bit0 is BOR (Brown-out).
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PIC16C62X TABLE 9-4: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter Condition STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0x MCLR Reset during normal operation 000h 000u uuuu ---- --uu MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 uuuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 000x xuuu ---- --u0 uuu1 0uuu ---- --uu Interrupt Wake-up from SLEEP PC + 1(1) Legend: u = unchanged, x = unkn
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PIC16C62X FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 9-9: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) FIGURE 9-10: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET  2003 Microchip Technology Inc.
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PIC16C62X FIGURE 9-11: VDD EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) FIGURE 9-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 VDD Q1 MCLR D R R2 R1 40k PIC16C62X MCLR PIC16C62X C Note 1: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device’s electrical specification.
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PIC16C62X 9.5 Interrupts The PIC16C62X has 4 sources of interrupt: • • • • External interrupt RB0/INT TMR0 overflow interrupt PORTB change interrupts (pins RB<7:4>) Comparator interrupt The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.
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PIC16C62X 9.5.1 RB0/INT INTERRUPT 9.5.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0. External interrupt on RB0/INT pin is edge triggered, either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
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PIC16C62X TABLE 9-6: SUMMARY OF INTERRUPT REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other RESETS(1) Address Name 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation. 9.
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PIC16C62X 9.7 Watchdog Timer (WDT) DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin.
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PIC16C62X 9.8 Power-Down Mode (SLEEP) The Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit in the STATUS register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hiimpedance).
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PIC16C62X 9.9 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 9.10 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify.
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PIC16C62X 10.0 INSTRUCTION SET SUMMARY Each PIC16C62X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C62X instruction set summary in Table 10-2 lists byte-oriented, bitoriented, and literal and control operations. Table 10-1 shows the opcode field descriptions.
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PIC16C62X TABLE 10-2: Mnemonic, Operands PIC16C62X INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to
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PIC16C62X 10.1 Instruction Descriptions Add Literal and W ANDLW AND Literal with W Syntax: [ label ] ADDLW Syntax: [ label ] ANDLW Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: C, DC, Z Status Affected: Z ADDLW Encoding: 11 k 111x kkkk kkkk Encoding: 11 k 1001 kkkk kkkk Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
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PIC16C62X BCF Bit Clear f Syntax: [ label ] BCF BTFSC Bit Test, Skip if Clear Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
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PIC16C62X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: Description: 01 bfff ffff If bit 'b' in register 'f' is '1', then the next instruction is skipped.
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PIC16C62X CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → (W) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 0001 0000 0011 Description: W register is cleared. Zero bit (Z) is set.
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PIC16C62X DECFSZ Decrement f, Skip if 0 INCF Increment f Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (dest); Operation: (f) + 1 → (dest) Status Affected: None Status Affected: Z Encoding: Description: 00 1011 skip if result = 0 dfff ffff The contents of register 'f' are decremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
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PIC16C62X INCFSZ Increment f, Skip if 0 IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Operation: (W) .OR. (f) → (dest) Status Affected: None Status Affected: Z Encoding: Description: 00 INCFSZ f,d 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register.
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PIC16C62X MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: Encoding: Description: MOVF f,d 00 1000 dfff ffff The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
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PIC16C62X RETFIE Return from Interrupt RETLW Return with Literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Encoding: Description: 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC16C62X RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Operation: See description below Status Affected: C Status Affected: C Encoding: Description: RLF 00 f,d 1101 dfff ffff The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in the W register.
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PIC16C62X SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k - (W) → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: C, DC, Z Operation: (f) - (W) → (dest) Status Affected: C, DC, Z Encoding: 00 Encoding: Description: 11 SUBLW k 110x kkkk kkkk The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
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PIC16C62X SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: Operands: 0 ≤ f ≤ 127 d ∈ [0,1] [ label ] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Operation: Status Affected: (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) None Encoding: Description: 00 Encoding: 1110 dfff ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register.
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PIC16C62X NOTES: DS30235J-page 74  2003 Microchip Technology Inc.
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PIC16C62X 11.
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PIC16C62X 11.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 11.
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PIC16C62X 11.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC16C62X 11.14 PICDEM 1 PICmicro Demonstration Board 11.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
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PIC16C62X 11.20 PICDEM 18R PIC18C601/801 Demonstration Board 11.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
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PIC16C62X NOTES: DS30235J-page 80  2003 Microchip Technology Inc.
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PIC16C62X 12.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Ambient Temperature under bias .............................................................................................................. -40° to +125°C Storage Temperature ................................................................................................................................ -65° to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.
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PIC16C62X PIC16C62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 12-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
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PIC16C62X PIC16C62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C FIGURE 12-3: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
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PIC16C62X FIGURE 12-5: PIC16LC620A/LC621A/LC622A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ 0°C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.7 2.5 2.0 0 4 10 Frequency (MHz) 20 25 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
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PIC16C62X PIC16CR62XA VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C FIGURE 12-7: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
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PIC16C62X PIC16LCR62XA VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 12-9: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. DS30235J-page 86  2003 Microchip Technology Inc.
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PIC16C62X FIGURE 12-10: PIC16C620A/C621A/C622A/CR620A - 40 VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 20 25 40 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
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PIC16C62X 12.
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PIC16C62X 12.1 DC Characteristics: PIC16C62X-04 (Commercial, Industrial, Extended) PIC16C62X-20 (Commercial, Industrial, Extended) PIC16LC62X-04 (Commercial, Industrial, Extended) (CONT.
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PIC16C62X 12.
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PIC16C62X 12.2 DC Characteristics: PIC16C62XA-04 (Commercial, Industrial, Extended) PIC16C62XA-20 (Commercial, Industrial, Extended) PIC16LC62XA-04 (Commercial, Industrial, Extended) (CONT.
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PIC16C62X 12.2 DC Characteristics: PIC16C62XA-04 (Commercial, Industrial, Extended) PIC16C62XA-20 (Commercial, Industrial, Extended) PIC16LC62XA-04 (Commercial, Industrial, Extended (CONT.
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PIC16C62X 12.3 DC CHARACTERISTICS: PIC16CR62XA-04 (Commercial, Industrial, Extended) PIC16CR62XA-20 (Commercial, Industrial, Extended) PIC16LCR62XA-04 (Commercial, Industrial, Extended) PIC16CR62XA-04 PIC16CR62XA-20 PIC16LCR62XA-04 Param. Sym No.
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PIC16C62X PIC16CR62XA-04 PIC16CR62XA-20 PIC16LCR62XA-04 Param. Sym No.
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PIC16C62X 12.3 DC CHARACTERISTICS: PIC16CR62XA-04 (Commercial, Industrial, Extended) PIC16CR62XA-20 (Commercial, Industrial, Extended) PIC16LCR62XA-04 (Commercial, Industrial, Extended) (CONT.) PIC16CR62XA-04 PIC16CR62XA-20 PIC16LCR62XA-04 Param. No.
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PIC16C62X 12.
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PIC16C62X 12.4 DC Characteristics: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended) PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended) (CONT.
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PIC16C62X 12.4 DC Characteristics: PIC16C62X/C62XA/CR62XA (Commercial, Industrial, Extended) PIC16LC62X/LC62XA/LCR62XA (Commercial, Industrial, Extended) (CONT.
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PIC16C62X 12.5 DC CHARACTERISTICS: PIC16C620A/C621A/C622A-40(7) (Commercial) PIC16CR620A-40(7) (Commercial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Param No. Sym Operating temperature Characteristic Min Typ† Max Units 0°C ≤ TA ≤ +70°C for commercial Conditions D001 D002 VDD VDR Supply Voltage RAM Data Retention Voltage(1) 3.0 — — 1.5* 5.
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PIC16C62X 12.5 DC CHARACTERISTICS: PIC16C620A/C621A/C622A-40(7) (Commercial) PIC16CR620A-40(7) (Commercial) DC CHARACTERISTICS Param No.
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PIC16C62X 12.6 PIC16C620A/C621A/C622A-40(3) (Commercial) PIC16CR620A-40(3) (Commercial) DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Power Supply Pins Operating temperature 0°C ≤ TA ≤ +70°C for commercial Sym Min Typ(1) Max Units VDD 4.5 — 5.5 V IDD — — 5.5 7.7 11.5 16 mA mA HS Oscillator Operating Frequency FOSC 20 — 40 Input Low Voltage OSC1 VIL VSS — 0.
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PIC16C62X TABLE 12-1: COMPARATOR SPECIFICATIONS Operating Conditions: VDD range as described in Table 12-1, -40°C
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PIC16C62X 12.8 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC16C62X 12.9 Timing Diagrams and Specifications FIGURE 12-12: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 12-3: Parameter No.
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PIC16C62X FIGURE 12-13: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 17 I/O Pin (output) 15 new value old value 20, 21 Note: All tests must be done with specified capacitance loads (Figure 12-11) 50 pF on I/O pins and CLKOUT.  2003 Microchip Technology Inc.
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PIC16C62X TABLE 12-4: Parameter No.
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PIC16C62X FIGURE 12-14: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins FIGURE 12-15: BROWN-OUT RESET TIMING BVDD VDD 35 TABLE 12-5: Parameter No. * † RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Sym Characteristic Min 2000 — — ns -40° to +85°C 7* 18 33* ms VDD = 5.
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PIC16C62X FIGURE 12-16: TIMER0 CLOCK TIMING RA4/T0CKI 41 40 42 TMR0 TABLE 12-6: Parameter No. 40 TIMER0 CLOCK REQUIREMENTS Sym Tt0H Characteristic T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period * † Min Typ† Max Units No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns No Prescaler 0.5 TCY + 20* — — ns With Prescaler 10* — — ns TCY + 40* N — — ns Conditions N = prescale value (1, 2, 4, ...
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PIC16C62X 13.0 DEVICE CHARACTERIZATION INFORMATION The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
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PIC16C62X FIGURE 13-3: IDD VS. VDD (XT OSC 4 MHZ) 1.00 0.9 0.8 IDD (mA) 0.7 0.6 0.5 0.4 0.3 0.2 2.5 3 3.5 4 4.5 5 5.5 VDD (VOLTS) IOI VS. VOL, VDD = 3.0V) FIGURE 13-4: 50 45 MAX -40°C 40 35 IOI (mA) TYP 25°C 30 MIN 85°C 25 20 15 10 5 0 0 .5 1 1.5 2 2.5 3 Vol (V) DS30235J-page 110  2003 Microchip Technology Inc.
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PIC16C62X FIGURE 13-5: IOH VS. VOH, VDD = 3.0V) 0 IOH (mA) -5 -10 MIN 85°C TYP 25°C -15 MAX -40°C -20 -25 0 .5 1 1.5 2 2.5 3 VOH (V) IOI VS. VOL, VDD = 5.5V) FIGURE 13-6: 100 MAX -40°C 90 80 TYP 25°C IOI (mA) 70 60 MIN 85°C 50 40 30 20 10 0 0 .5 1 1.5 2 2.5 3 Vol (V)  2003 Microchip Technology Inc.
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PIC16C62X FIGURE 13-7: IOH VS. VOH, VDD = 5.5V) 0 IOH (mA) -10 -20 MIN 85°C -30 TYP 25°C -40 MAX -40°C -50 3 3.5 4 4.5 5 5.5 VOH (V) DS30235J-page 112  2003 Microchip Technology Inc.
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PIC16C62X 14.0 PACKAGING INFORMATION 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
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PIC16C62X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .300 .313 .
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PIC16C62X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .091 .
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PIC16C62X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .
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PIC16C62X 14.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX AABBCDE 18-Lead SOIC (.300") XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX AABBCDE PIC16C622A -04I / P456 9923CBA Example PIC16C622 -04I / S0218 9918CDK 18-Lead CERDIP Windowed Example XXXXXXXX XXXXXXXX AABBCDE 20-Lead SSOP XXXXXXXXXX XXXXXXXXXX AABBCDE Legend: Note: * XX...
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PIC16C62X NOTES: DS30235J-page 118  2003 Microchip Technology Inc.
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PIC16C62X APPENDIX A: ENHANCEMENTS APPENDIX B: COMPATIBILITY The following are the list of enhancements over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Instruction word length is increased to 14 bits.
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PIC16C62X NOTES: DS30235J-page 120  2003 Microchip Technology Inc.
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PIC16C62X INDEX A ADDLW Instruction ............................................................. 63 ADDWF Instruction ............................................................. 63 ANDLW Instruction ............................................................. 63 ANDWF Instruction ............................................................. 63 Architectural Overview .......................................................... 9 Assembler MPASM Assembler.....................................................
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PIC16C62X N V NOP Instruction................................................................... 69 Voltage Reference Module ................................................. 43 VRCON Register ................................................................ 43 O One-Time-Programmable (OTP) Devices............................. 7 OPTION Instruction............................................................. 69 OPTION Register ................................................................
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PIC16C62X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site.
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PIC16C62X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16C62X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X Device Frequency Range Temperature Range /XX XXX Package Pattern Device PIC16C62X: VDD range 3.0V to 6.0V PIC16C62XT: VDD range 3.0V to 6.0V (Tape and Reel) PIC16C62XA: VDD range 3.0V to 5.5V PIC16C62XAT: VDD range 3.0V to 5.5V (Tape and Reel) PIC16LC62X: VDD range 2.5V to 6.0V PIC16LC62XT: VDD range 2.5V to 6.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Marketing Support Division Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K.