Datasheet

PIC16C55X
DS40143E-page 44 Preliminary  1996-2013 Microchip Technology Inc.
FIGURE 6-13: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 6-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR
Value on all
other RESETS
2007h Config. bits
— Reserved CP1 CP0 PWRTE WDTE FOSC1 FOSC0
81h OPTION
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’.
Shaded cells are not used by the Watchdog Timer.
Postscaler
M
U
X
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
From TMR0 Clock Source
(Figure 7-6)
Watchdog
Timer
WDT
Enable Bit
0
1
PSA
8 - to - 1 MUX
8
PS<2:0>
To TMR0
(Figure 7-6)
01
PSA
WDT
Timeout
MUX