PIC16C55X EPROM-Based 8-Bit CMOS Microcontrollers Devices Included in this Data Sheet: Pin Diagram Referred to collectively as PIC16C55X.
PIC16C55X Special Microcontroller Features: • Power-on Reset (POR) • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Programmable code protection • Power saving SLEEP mode • Selectable oscillator options • Serial in-circuit programming (via two pins) • Four user programmable ID locations Note: For additional information on enhancements, see Appendix A CMOS Technology: • Low power, high speed CMOS EPROM technology
PIC16C55X Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7 3.0 Architectural Overview ................................................................................
PIC16C55X NOTES: DS40143E-page 4 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 1.0 GENERAL DESCRIPTION The PIC16C55X are 18, 20 and 28-Pin EPROM-based members of the versatile PIC16CXX family of low cost, high performance, CMOS, fully-static, 8-bit microcontrollers. All PIC® microcontrollers employ an advanced RISC architecture. The PIC16C55X have enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources.
PIC16C55X TABLE 1-1: Clock Memory Peripherals PIC16C55X FAMILY OF DEVICES PIC16C554 PIC16C557 PIC16C558 Maximum Frequency of Operation (MHz) 20 20 20 EPROM Program Memory (x14 words) 512 2K 2K Data Memory (bytes) 80 128 128 Timer Module(s) TMR0 TMR0 TMR0 Interrupt Sources 3 3 3 I/O Pins Features Voltage Range (Volts) Brown-out Reset Packages 13 22 13 2.5-5.5 2.5-5.5 2.5-5.
PIC16C55X 2.0 PIC16C55X DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C55X Product Identification System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.
PIC16C55X NOTES: DS40143E-page 8 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C55X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C55X uses a Harvard architecture in which program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory.
PIC16C55X FIGURE 3-1: BLOCK DIAGRAM Device Program Memory PIC16C554 512 x 14 80 x 8 PIC16C557 2 K x 14 128 x 8 PIC16C558 2 K x 14 128 x 8 EPROM Data Memory 13 Program Memory 512 x 14 to 2K x 14 Program Bus PORTA RA0 RA1 RA2 RA3 RAM File Registers 80 x 8 to 128 x 8 8-Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr(1) RA4/T0CKI PORTB 8 Addr MUX Instruction reg 7 Direct Addr 8 RB0/INT Indirect Addr RB7:RB1 FSR STATUS reg 8 3 Power-up Timer Instruction Decode & Con
PIC16C55X TABLE 3-1: PIC16C55X PINOUT DESCRIPTION Pin Number Name PDIP SOIC SSOP Pin Type Buffer Type Description OSC1/CLKIN 16 16 18 I OSC2/CLKOUT 15 15 17 O ST/CMOS Oscillator crystal input/external clock source output. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
PIC16C55X 3.1 Clocking Scheme/Instruction Cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4.
PIC16C55X 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization FIGURE 4-2: The PIC16C55X has a 13-bit program counter capable of addressing an 8 K x 14 program memory space. Only the first 512 x 14 (0000h - 01FFh) for the PIC16C554 and 2K x 14 (0000h - 07FFh) for the PIC16C557 and PIC16C558 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 512 x 14 spaces in the PIC16C554, or 2K x 14 space of the PIC16C558 and PIC16C557.
PIC16C55X FIGURE 4-3: DATA MEMORY MAP FOR THE PIC16C554 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 6Fh INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PCLATH INTCON PCON FIGURE 4-4: File Address File Address 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh 00h 01h 02h 0
PIC16C55X FIGURE 4-5: DATA MEMORY MAP FOR THE PIC16C558 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) OPTION PCL STATUS FSR TRISA TRISB PCLATH INTCON PCLATH INTCON PCON General Purpose Register General Purpose Register 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh
PIC16C55X TABLE 4-1: Address SPECIAL REGISTERS FOR THE PIC16C55X Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Detail on POR Reset Page: Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 21 01h TMR0 Timer0 Module’s Register xxxx xxxx 47 02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 21 03h STATUS 04h FSR 05h PORTA IRP(2) RP1(2) RP0 TO PD Z DC C Indirect data memory
PIC16C55X 4.2.2.1 STATUS Register It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect any status bits. For other instructions, not affecting any status bits, see the “Instruction Set Summary”. The STATUS register, shown in Figure 4-2, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.
PIC16C55X 4.2.2.2 OPTION Register Note 1: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). The OPTION register is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB.
PIC16C55X 4.2.2.3 INTCON Register The INTCON register is a readable and writable register which contains the various enable and flag bits for all interrupt sources. REGISTER 4-3: Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16C55X 4.2.2.4 PCON Register The PCON register contains a flag bit to differentiate between a Power-on Reset, an external MCLR Reset or WDT Reset. See Section 6.3 and Section 6.4 for detailed RESET operation.
PIC16C55X 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high bits (PC<12:8>) are not directly readable or writable and come from PCLATH. On any RESET, the PC is cleared. Figure 4-6 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16C55X FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16C55X Direct Addressing (1) from opcode RP1 RP0 6 bank select location select Indirect Addressing IRP(1) 0 7 bank select 00 01 10 FSR register 0 location select 11 00h 00h not used Data Memory 7Fh 7Fh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-3 and Figure 4-5. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear. DS40143E-page 22 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 5.0 I/O PORTS FIGURE 5-2: The PIC16C554 and PIC16C558 have two ports, PORTA and PORTB. The PIC16C557 has three ports, PORTA, PORTB and PORTC. 5.1 PORTA and TRISA Registers Data bus WR PORTA PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open-drain output. Port RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers.
PIC16C55X TABLE 5-1: PORTA FUNCTIONS Name Bit # Buffer Type RA0 RA1 RA2 RA3 RA4/T0CKI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 ST ST ST ST ST Function Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port. Bi-directional I/O port or external clock input for TMR0. Output is open drain type.
PIC16C55X 5.2 PORTB and TRISB Registers latched in INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner: PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s).
PIC16C55X FIGURE 5-4: BLOCK DIAGRAM OF RB3:RB0 PINS RBPU(1) VDD VDD Data Latch Data Bus D WR PORTB Q weak P pull-up VDD P CK D WR TRISB I/O pin N TRIS Latch Q CK VSS VSS Q TTL ST Input Buffer Buffer RD TRISB Latch Q D EN RD PORTB RB0/INT ST Buffer RD PORTB Note 1: TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION<7>). TABLE 5-3: Name PORTB FUNCTIONS Bit # Buffer Type RB0/INT Bit 0 TTL/ST(1) Bi-directional I/O port. Internal software programmable weak pull-up.
PIC16C55X 5.3 PORTC and TRISC Registers(1) FIGURE 5-5: PORTC is a 8-bit wide latch. All pins have data direction bits (TRIS registers) which can configure these pins as input or output. BLOCK DIAGRAM OF PORT PINS RC<7:0> Data Bus D A '1' in the TRISC register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISC register puts the contents of the output latch on the selected pin(s).
PIC16C55X 5.4 5.4.1 I/O Programming Considerations BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC16C55X EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT 5.4.2 The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle, as shown in Figure 5-6. Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port.
PIC16C55X NOTES: DS40143E-page 30 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 6.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C55X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 6.
PIC16C55X REGISTER 6-1: CP1 CONFIGURATION WORD CP0 CP1 CP0 CP1 CP0 — Reserved CP1 CP0 PWRTE WDTE F0SC1 bit 13 bit 13-8 bit 5-4 bit 7 F0SC0 bit 0 CP<1:0>: Code protection bits(1) 11 = Program Memory code protection off 10 = 0400h - 07FFh code protected 01 = 0200h - 07FFh code protected 11 = 0000h - 07FFh code protected Unimplemented: Read as '1' bit 6 Reserved: Do not use bit 3 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 2 WDTE: Watchdog Timer Enable bit 1 =
PIC16C55X 6.2 TABLE 6-1: Oscillator Configurations 6.2.1 OSCILLATOR TYPES The PIC16C55X can be operated in four different oscillator options. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 6.2.
PIC16C55X 6.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a pre-packaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. Figure 6-3 shows implementation of a parallel resonant oscillator circuit.
PIC16C55X 6.3 RESET The PIC16C55X differentiates between various kinds of RESET: • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (normal operation) WDT wake-up (SLEEP) A simplified block diagram of the on-chip RESET circuit is shown in Figure 6-6. The MCLR Reset path has a noise filter to detect and ignore small pulses. See Table 10-3 for pulse width specification.
PIC16C55X 6.4 6.4.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.6V – 1.8V). To take advantage of the POR, just tie the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Electrical Specifications for details.
PIC16C55X 6.4.5 POWER CONTROL/STATUS REGISTER (PCON) Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset. On a subsequent RESET if POR is ‘0’, it will indicate that a Poweron Reset must have occurred (VDD may have gone too low).
PIC16C55X TABLE 6-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 000h 0001 1xxx ---- --0- MCLR Reset during normal operation 000h 000u uuuu ---- --u- MCLR Reset during SLEEP 000h 0001 0uuu ---- --u- WDT Reset 000h 0000 uuuu ---- --u- PC + 1 uuu0 0uuu ---- --u- uuu1 0uuu ---- --u- Condition WDT Wake-up Interrupt Wake-up from SLEEP PC + 1(1) Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q =
PIC16C55X FIGURE 6-7: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 6-8: VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET 1996-2013 Microchip Technology Inc.
PIC16C55X FIGURE 6-9: TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3 VDD MCLR INTERNAL POR TPWRT PWRT TIMEOUT TOST OST TIMEOUT INTERNAL RESET FIGURE 6-10: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD D R R1 MCLR C Note 1: 2: 3: PIC16C55X External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down.
PIC16C55X 6.5 Interrupts The PIC16C55X has 3 sources of interrupt: • External interrupt RB0/INT • TMR0 overflow interrupt • PORTB change interrupts (pins RB7:RB4) The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts.
PIC16C55X 6.5.1 RB0/INT INTERRUPT 6.5.2 An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 7.0. An external interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set, or falling if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
PIC16C55X 6.6 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and STATUS register). This will have to be implemented in software. Example 6-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e.
PIC16C55X FIGURE 6-13: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 7-6) 0 Watchdog Timer M U X 1 Postscaler 8 PS<2:0> 8 - to - 1 MUX PSA WDT Enable Bit To TMR0 (Figure 7-6) 0 1 MUX PSA WDT Timeout Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. TABLE 6-7: Address SUMMARY OF WATCHDOG TIMER REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 2007h Config.
PIC16C55X 6.8 Power-Down Mode (SLEEP) The first event will cause a device RESET. The two latter events are considered a continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device RESET. PD bit, which is set on power-up is cleared when SLEEP is invoked. TO bit is cleared if WDT Wake-up occurred. The Power-down mode is entered by executing a SLEEP instruction.
PIC16C55X 6.9 FIGURE 6-15: Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 6.10 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers.
PIC16C55X 7.0 TIMER0 MODULE bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The Timer0 module timer/counter has the following features: • • • • • • The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable.
PIC16C55X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 PC PC+1 MOVWF TMR0 Instruction Fetch T0 TMR0 PC+2 PC+3 T0+1 Instruction Execute MOVF TMR0,W PC+5 PC+6 MOVF TMR0,W NT0+1 NT0 Write TMR0 executed FIGURE 7-4: PC+4 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0 Read TMR0 reads NT0
PIC16C55X 7.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output.
PIC16C55X FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER Data Bus CLKOUT (=Fosc/4) 0 T0CKI pin 8 M U X 1 M U X 0 1 SYNC 2 Tcy TMR0 reg T0SE T0CS 0 Watchdog Timer 1 M U X Set flag bit T0IF on Overflow PSA 8-bit Prescaler 8 8-to-1MUX PS0 - PS2 PSA WDT Enable bit 0 1 MUX PSA WDT Timeout Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register. DS40143E-page 50 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 7.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 7-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to WDT.
PIC16C55X NOTES: DS40143E-page 52 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 8.0 INSTRUCTION SET SUMMARY Each PIC16C55X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16C55X instruction set summary in Table 8-2 lists byte-oriented, bitoriented, and literal and control operations. Table 81 shows the opcode field descriptions. For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator.
PIC16C55X TABLE 8-2: Mnemonic, Operands PIC16C55X INSTRUCTION SET 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f
PIC16C55X 8.1 Instruction Descriptions ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: ANDLW AND Literal with W Syntax: [ label ] ANDLW 0 k 255 Operands: 0 k 255 Operation: (W) + k (W) Operation: (W) .AND. (k) (W) Status Affected: C, DC, Z Status Affected: Z Encoding: 11 Encoding: 11 Description: 111x k kkkk kkkk The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC16C55X BCF Bit Clear f Syntax: [ label ] BCF Operands: BTFSC Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: Description: 01 f,b Bit Test, Skip if Clear 00bb bfff Words: 1 Cycles: 1 Example BCF BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 Operation: 1 (f) Status Affected: None Encoding: 01 01bb Words: 1 Cyc
PIC16C55X BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 f 127 0b<7 Operands: 0 k 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Encoding: Description: 01 bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped.
PIC16C55X CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h (W) 1Z 0 f 127 d [0,1] Operation: (f) (dest) Z Status Affected: Z Status Affected: Encoding: Description: 00 0001 0000 0011 W register is cleared. Zero bit (Z) is set.
PIC16C55X DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 2047 Operation: Operation: (f) - 1 (dest); k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Status Affected: None Encoding: Description: 00 1011 skip if result = 0 dfff ffff Encoding: GOTO k 10 1kkk kkkk kkkk The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the W register.
PIC16C55X INCFSZ Increment f, Skip if 0 Syntax: [ label ] Operands: IORWF Syntax: [ label ] 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (dest), skip if result = 0 Operation: (W) .OR. (f) (dest) Status Affected: None Status Affected: Z Encoding: Description: 00 INCFSZ f,d Inclusive OR W with f 1111 dfff ffff The contents of register 'f' are incremented. If 'd' is 0 the result is placed in the W register.
PIC16C55X MOVF Move f NOP Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) (dest) Status Affected: Z Encoding: Description: MOVF f,d 1000 dfff ffff The contents of register f is moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected.
PIC16C55X RETFIE Return from Interrupt Syntax: [ label ] Operands: Operation: Status Affected: RETFIE [ label ] None Operands: None TOS PC, 1 GIE Operation: TOS PC Status Affected: None None 00 Encoding: 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16C55X RRF Rotate Right f through Carry Syntax: [ label ] Operands: Subtract W from Literal Syntax: [ label ] SUBLW k 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below C, DC, Z Status Affected: C Status Affected: Encoding: Description: RRF f,d SUBLW 00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0 the result is placed in the W register.
PIC16C55X SUBWF Subtract W from f Syntax: [ label ] Operands: SWAPF Syntax: [ label ] SWAPF f,d 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - (W) dest) Operation: Status Affected: C, DC, Z (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) Status Affected: None Encoding: 00 SUBWF f,d Swap Nibbles in f 0010 dfff ffff Encoding: 00 1110 dfff ffff Description: Subtract (2’s complement method) W register from register 'f'.
PIC16C55X XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description: The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C55X NOTES: DS40143E-page 66 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 9.
PIC16C55X 9.4 MPLINK Object Linker/ MPLIB Object Librarian 9.6 The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16C55X 9.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC MCUs and can be used to develop for this and other PIC microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC16C55X 9.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X PIC16C7XX PIC16C8X PIC16F8XX PIC16C9XX 1996-2013 Microchip Technology Inc. Preliminary ** † † MCP2510 † * Contact the Microchip Technology Inc. web site at www.microchip.
PIC16C55X NOTES: DS40143E-page 72 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 10.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings † Ambient Temperature under bias ...............................................................................................................-40to +125C Storage Temperature ................................................................................................................................ -65 to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) .......................................................-0.
PIC16C55X VOLTAGE-FREQUENCY GRAPH, 0C TA +70C (COMMERCIAL TEMPS) FIGURE 10-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16C55X VOLTAGE-FREQUENCY GRAPH, 0C TA +85C FIGURE 10-3: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16C55X 10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended) PIC16C55X-20 (Commercial, Industrial, Extended) HCS1365-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended DC Characteristics Param No. Sym VDD Characteristic Min Typ† Max Units Conditions Supply Voltage D001 16LC55X 3.0 2.5 — 5.5 5.
PIC16C55X 10.1 DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended) PIC16C55X-20 (Commercial, Industrial, Extended) HCS1365-04 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended DC Characteristics Param No. D020 Sym IPD IWDT * Characteristic Min Typ† Max Units Conditions Power-Down Current(3) 16LC55X — 0.
PIC16C55X 10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X(Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial and -40°C TA +125°C for automotive Operating voltage VDD range as described in DC spec Table 10-1 DC Characteristics Param. No. Sym VIL Characteristic Min Typ† Max Unit with TTL buffer VSS — 0.8V 0.
PIC16C55X 10.2 DC Characteristics: PIC16C55X (Commercial, Industrial, Extended) PIC16LC55X(Commercial, Industrial, Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial and 0°C TA +70°C for commercial and -40°C TA +125°C for automotive Operating voltage VDD range as described in DC spec Table 10-1 DC Characteristics Param. No. Sym D092 * VOD Characteristic Min Typ† Max Unit VDD-0.7 — — V IOH=-2.
PIC16C55X 10.3 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16C55X 10.4 Timing Diagrams and Specifications FIGURE 10-6: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic Min Fos External CLKIN Frequency(1) DC — 4 MHz XT and RC osc mode, VDD=5.
PIC16C55X FIGURE 10-7: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 10 11 22 23 CLKOUT 13 19 14 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note 1: All tests must be done with specified capacitance loads (Figure 10-5) 50 pF on I/O pins and CLKOUT. DS40143E-page 82 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X TABLE 10-2: Parameter # CLKOUT AND I/O TIMING REQUIREMENTS Sym Characteristic Min Typ† Max Units 10* TosH2ckL OSC1 to CLKOUT (1) — — 75 — 200 400 ns ns 11* TosH2ckH OSC1 to CLKOUT (1) — — 75 — 200 400 ns ns 12* TckR CLKOUT rise time(1) — — 35 — 100 200 ns ns 13* TckF CLKOUT fall time(1) — — 35 — 100 200 ns ns 14* TckL2ioV CLKOUT to Port out valid(1) — — 20 ns 15* TioV2ckH Port in valid before CLKOUT Tosc +200 ns Tosc +400 ns — — — — ns ns
PIC16C55X FIGURE 10-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 34 I/O Pins TABLE 10-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Param No.
PIC16C55X FIGURE 10-9: TIMER0 CLOCK TIMING RA4/T0CKI 41 40 42 TMR0 TABLE 10-4: TIMER0 CLOCK REQUIREMENTS Param No. Sym 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width Characteristic No Prescaler Min Typ† Max Units 0.5 TCY + 20* — — ns With Prescaler No Prescaler 10* — — ns 0.5 TCY + 20* — — ns 10* — — ns TCY + 40* N — — ns With Prescaler 42 Tt0P T0CKI Period Conditions N = prescale value (1, 2, 4, ...
PIC16C55X NOTES: DS40143E-page 86 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X 11.0 PACKAGING INFORMATION 11.1 Package Marking Information 18-Lead PDIP Example PIC16C558 -04I / P456 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead PDIP 9823 CBA Example PIC16C557 -04I / P456 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP 9823 CBA Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16C558 -04/SS218 0020 CBP 28-Lead SSOP Example PIC16C557 -04I / SS123 XXXXXXXXXXXX XXXXXXXXXXXX 0025 CBA YYWWNNN Legend: XX...
PIC16C55X Package Marking Information (Cont’d) 18-Lead SOIC (.300”) Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC16C558 -04I / S0218 9818 CDK 28-Lead SOIC (.
PIC16C55X 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c A1 B1 p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .
PIC16C55X 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 2.54 .100 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.
PIC16C55X 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C55X 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C55X 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C55X 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D W2 2 n 1 W1 E A2 A c L Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC16C55X 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C55X 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC16C55X APPENDIX A: ENHANCEMENTS APPENDIX B: COMPATIBILITY The following are the list of enhancements over the PIC16C5X microcontroller family: To convert code written for PIC16C5X to PIC16C55X, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. Instruction word length is increased to 14 bits.
PIC16C55X NOTES: DS40143E-page 98 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X INDEX A ADDLW Instruction ............................................................. 55 ADDWF Instruction ............................................................. 55 ANDLW Instruction ............................................................. 55 ANDWF Instruction ............................................................. 55 Architectural Overview .......................................................... 9 Assembler MPASM Assembler ....................................................
PIC16C55X PICSTART Plus Entry Level Development Programmer .... 69 Port RB Interrupt ................................................................. 42 PORTA................................................................................ 23 PORTB.......................................................................... 25, 27 Power Control/Status Register (PCON) .............................. 37 Power-Down Mode (SLEEP)............................................... 45 Power-On Reset (POR) ................
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PIC16C55X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device X Temperature Range /XX XXX Package Pattern Examples: a) PIC17C756–16L Commercial Temp., PLCC package, 16 MHz, normal VDD limits b) PIC17LC756–08/PT Commercial Temp., TQFP package, 8MHz, extended VDD limits c) PIC17C756–33I/PT Industrial Temp.
PIC16C55X NOTES: DS40143E-page 104 Preliminary 1996-2013 Microchip Technology Inc.
PIC16C55X NOTES: 1996-2013 Microchip Technology Inc.
PIC16C55X DS40143E-page 106 Preliminary 1996-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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