Datasheet

 1999-2012 Microchip Technology Inc. DS40192D-page 67
PIC16C505
FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505
TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505
TABLE 10-6: DRT (DEVICE RESET TIMER PERIOD - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0C  T
A  +70C (commercial)
–40C  T
A  +85C (industrial)
–40C  T
A  +125C (extended)
Operating Voltage V
DD range is described in Section 10.1
Parameter
No. Sym Characteristic Min Typ
(1)
Max Units Conditions
30
TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5.0 V
31
Twdt Watchdog Timer Time-out Period
(No Prescaler)
9* 18* 30* ms VDD = 5.0 V (Commercial)
32
TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5.0 V (Commercial)
34
TioZ I/O Hi-impedance from MCLR Low — — 2000* ns
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Oscillator Configuration POR Reset Subsequent Resets
IntRC & ExtRC 18 ms (typical) 300 µs (typical)
XT, HS & LP 18 ms (typical) 18 ms (typical)
VDD
MCLR
Internal
POR
DRT
Timeout
Internal
RESET
Watchdog
Timer
RESET
32
31
34
I/O pin
32
32
34
(Note 1)
30
(Note 2)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR
or WDT reset only in XT, LP and HS modes.