Datasheet

PIC16C505
DS40192D-page 32  1999-2012 Microchip Technology Inc.
7.3.1 MCLR ENABLE
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR
function. When
programmed, the MCLR
function is tied to the internal
V
DD, and the pin is assigned to be a I/O. See
Figure 7-6.
FIGURE 7-6: MCLR SELECT
7.4 Power-On Reset (POR)
The PIC16C505 family incorporates on-chip Power-On
Reset (POR) circuitry, which provides an internal chip
reset for most power-up situations.
The on chip POR circuit holds the chip in reset until V
DD
has reached a high enough level for proper operation.
To take advantage of the internal POR, program the
RB3/MCLR/VPP pin as MCLR and tie through a resistor
to V
DD or program the pin as RB3. An internal weak
pull-up resistor is implemented using a transistor. Refer
to Table 10-1 for the pull-up resistor ranges. This will
eliminate external RC components usually needed to
create a Power-on Reset. A maximum rise time for VDD
is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-7.
RB3/MCLR/VPP
MCLRE
INTERNAL MCLR
WEAK
PULL-UP
RBWU
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR
is held low is
shown in Figure 7-8. V
DD is allowed to rise and
stabilize before bringing MCLR
high. The chip will
actually come out of reset T
DRT msec after MCLR
goes high.
In Figure 7-9, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be RB3.). The V
DD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However,
Figure 7-10 depicts a problem situation where V
DD
rises too slowly. The time between when the DRT
senses that MCLR
is high and when MCLR and VDD
actually reach their full value, is too long. In this
situation, when the start-up timer times out, V
DD has
not reached the V
DD (min) value and the chip may not
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-9).
For additional information refer to Application Notes
“
Power-Up Considerations” - AN522 and “ Power-up
Trouble Shooting
” - AN607.
Note: When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, tempera-
ture, etc.) must be met to ensure operation.
If these conditions are not met, the device
must be held in reset until the operating
conditions are met.