PIC16C505 14-Pin, 8-Bit CMOS Microcontroller Device included in this Data Sheet: Special Microcontroller Features: PIC16C505 • • • • High-Performance RISC CPU: • Only 33 instructions to learn • Operating speed: - DC - 20 MHz clock input - DC - 200 ns instruction cycle Memory Device PIC16C505 Program Data 1024 x 12 72 x 8 • Direct, indirect and relative addressing modes for data and instructions • 12-bit wide instructions • 8-bit wide data path • 2-level deep hardware stack • Eight special function
PIC16C505 TABLE OF CONTENTS 1.0 General Description..................................................................................................................................................................... 3 2.0 PIC16C505 Device Varieties ....................................................................................................................................................... 5 3.0 Architectural Overview .................................................................................
PIC16C505 1.0 GENERAL DESCRIPTION The PIC16C505 from Microchip Technology is a lowcost, high-performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontroller. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 s) except for program branches, which take two cycles. The PIC16C505 delivers performance an order of magnitude higher than its competitors in the same price category.
PIC16C505 TABLE 1-1: PIC16C505 DEVICE PIC16C505 Clock Memory Peripherals Features Maximum Frequency of Operation (MHz) 20 EPROM Program Memory 1024 Data Memory (bytes) 72 Timer Module(s) TMR0 Wake-up from SLEEP on pin change Yes I/O Pins 11 Input Pins 1 Internal Pull-ups Yes In-Circuit Serial Programming Yes Number of Instructions 33 Packages 14-pin DIP, SOIC, TSSOP The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect, high I/O current capabi
PIC16C505 2.0 PIC16C505 DEVICE VARIETIES A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C505 Product Identification System at the back of this data sheet to specify the correct part number. 2.
PIC16C505 NOTES: DS40192D-page 6 1999-2012 Microchip Technology Inc.
PIC16C505 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16C505 can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C505 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus.
PIC16C505 FIGURE 3-1: PIC16C505 BLOCK DIAGRAM 12 Program Bus Data Bus Program Counter EPROM 1K x 12 Program Memory 8 12 RAM Addr 9 Addr MUX Instruction reg Indirect 5-7 Addr 5 FSR reg STATUS reg 8 3 Device Reset Timer Instruction Decode & Control OSC1/CLKIN OSC2 Timing Generation RB0 RB1 RB2 RB3/MCLR/VPP RB4/OSC2/CLKOUT RB5/OSC1/CLKIN RAM 72 bytes File Registers STACK1 STACK2 Direct Addr PORTB Power-on Reset PORTC RC0 RC1 RC2 RC3 RC4 RC5/T0CKI MUX ALU 8 Watchdog Timer W reg Inte
PIC16C505 TABLE 3-1: PIC16C505 PINOUT DESCRIPTION DIP Pin # SOIC Pin # I/O/P Type RB0 13 13 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode. RB1 12 12 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change.
PIC16C505 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
PIC16C505 4.0 MEMORY ORGANIZATION PIC16C505 memory is organized into program memory and data memory. For the PIC16C505, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. Data memory banks are accessed using the File Select Register (FSR). 4.1 FIGURE 4-1: PC<11:0> 12 CALL, RETLW Stack Level 1 Stack Level 2 Program Memory Organization The PIC16C505 devices have a 12-bit Program Counter (PC).
PIC16C505 4.2 Data Memory Organization For the PIC16C505, the register file is composed of 8 Special Function Registers, 24 General Purpose Registers and 48 General Purpose Registers that may be addressed using a banking scheme (Figure 4-2). Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers and General Purpose Registers. 4.2.
PIC16C505 4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets. The Special Function Registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1).
PIC16C505 4.3 STATUS Register For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). This register contains the arithmetic status of the ALU, the RESET status and the page preselect bit. It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register, because these instructions do not affect the Z, DC or C bits from the STATUS register.
PIC16C505 4.4 OPTION Register Note: The OPTION register is a 8-bit wide, write-only register, which contains various control bits to configure the Timer0/WDT prescaler and Timer0. If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides OPTION control of RBPU and RBWU). By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits.
PIC16C505 4.5 OSCCAL Register The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part, so it can be reprogrammed correctly later. After you move in the calibration constant, do not change the value. See Section 7.2.
PIC16C505 4.6 Program Counter 4.6.1 EFFECTS OF RESET As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. The Program Counter is set upon a RESET, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction.
PIC16C505 4.8 Indirect Data Addressing; INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16C505 5.0 I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. 5.1 PORTB PORTB is an 8-bit I/O register. Only the low order 6 bits are used (RB<5:0>). Bits 7 and 6 are unimplemented and read as '0's.
PIC16C505 TABLE 5-1: Address SUMMARY OF PORT REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets N/A TRISB — — I/O control registers --11 1111 --11 1111 N/A TRISC — — I/O control registers --11 1111 --11 1111 N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 1111 1111 1111 1111 03h STATUS RBWUF — PAO TO PD Z DC C 0001 1xxx q00q quuu(1) 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 --xx xxxx --uu
PIC16C505 FIGURE 5-2: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF PORTB PC + 1 MOVF PORTB,W Q1 Q2 Q3 Q4 PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle. RB<5:0> TPD = propagation delay Port pin written here Instruction executed MOVWF PORTB (Write to PORTB) 1999-2012 Microchip Technology Inc.
PIC16C505 NOTES: DS40192D-page 22 1999-2012 Microchip Technology Inc.
PIC16C505 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.
PIC16C505 FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Instruction Fetch MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W PC-1 T0 Timer0 PC PC+1 T0+1 PC+3 T0+2 Instruction Executed Write TMR0 executed FIGURE 6-3: PC+2 PC+4 PC+5 NT0+1 NT0 Read TMR0 Read TMR0 reads NT0 reads NT0 Read TMR0 reads NT0 PC+6 NT0+2 Read TMR0 Read TMR0 reads NT0
PIC16C505 6.1 Using Timer0 with an External Clock When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value.
PIC16C505 6.2 Prescaler RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (Section 7.6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both.
PIC16C505 7.0 SPECIAL FEATURES OF THE CPU The PIC16C505 has a Watchdog Timer, which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS, XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC, there is an 18 ms delay only on VDD power-up.
PIC16C505 7.2 Oscillator Configurations 7.2.1 OSCILLATOR TYPES TABLE 7-1: The PIC16C505 can be operated in four different oscillator modes. The user can program three configuration bits (FOSC<2:0>) to select one of these four modes: • • • • • LP: XT: HS: INTRC: EXTRC: 7.2.2 Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Internal 4 MHz Oscillator External Resistor/Capacitor Osc Type CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION) C1(1) OSC1 Cap.
PIC16C505 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.
PIC16C505 7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see Electrical Specifications section for information on variation over voltage and temperature. In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always protected, regardless of the code protect settings.
PIC16C505 TABLE 7-3: RESET CONDITIONS FOR REGISTERS Address Power-on Reset MCLR Reset WDT time-out Wake-up on Pin Change — qqqq qqqq(1) qqqq qqqq(1) 00h xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx q00q quuu(2,3) FSR 04h 110x xxxx 11uu uuuu OSCCAL 05h 1000 00-- uuuu uu-- PORTB 06h --xx xxxxx --uu uuuu PORTC 07h --xx xxxxx --uu uuuu OPTION — 1111 1111 1111 1111 TRISB — --11 1111 --11 1111 TRISC — --11 1111 --
PIC16C505 7.3.1 MCLR ENABLE This configuration bit when unprogrammed (left in the ‘1’ state) enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD, and the pin is assigned to be a I/O. See Figure 7-6. FIGURE 7-6: MCLR SELECT RBWU MCLRE WEAK PULL-UP INTERNAL MCLR RB3/MCLR/VPP 7.4 Power-On Reset (POR) The PIC16C505 family incorporates on-chip Power-On Reset (POR) circuitry, which provides an internal chip reset for most power-up situations.
PIC16C505 FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Power-Up Detect POR (Power-On Reset) VDD Pin Change Wake-up on pin change SLEEP RB3/MCLR/VPP WDT Time-out MCLRE RESET 8-bit Asynch On-Chip DRT OSC S Q R Q Ripple Counter (Start-Up Timer) CHIP RESET FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDR
PIC16C505 FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET Note: 7.5 When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min. Device Reset Timer (DRT) In the PIC16C505, the DRT runs any time the device is powered up.
PIC16C505 7.6.1 WDT PERIOD 7.6.2 The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-topart process variations (see DC specs).
PIC16C505 7.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/RBWUF) FIGURE 7-13: BROWN-OUT PROTECTION CIRCUIT 2 VDD The TO, PD, and RBWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) reset.
PIC16C505 7.9 Power-Down Mode (SLEEP) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 7.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or hi-impedance).
PIC16C505 7.12 In-Circuit Serial Programming The PIC16C505 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
PIC16C505 8.0 INSTRUCTION SET SUMMARY Each PIC16C505 instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C505 instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions.
PIC16C505 TABLE 8-2: INSTRUCTION SET SUMMARY Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f,d f,d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d 12-Bit Opcode Description Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract
PIC16C505 ADDWF Add W and f Syntax: [ label ] ADDWF ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 f 31 d Operands: 0 f 31 d Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest) f,d Status Affected: C, DC, Z Encoding: 0001 Description: Status Affected: Z 11df ffff Encoding: 0001 Add the contents of the W register and register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is '1', the result is stored back in register 'f'.
PIC16C505 BSF Bit Set f Syntax: [ label ] BSF BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 f 31 0b7 Operands: 0 f 31 0b<7 Operation: 1 (f) Operation: skip if (f) = 1 f,b Status Affected: None Encoding: Description: Status Affected: None 0101 bbbf ffff Bit 'b' in register 'f' is set.
PIC16C505 CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 k 255 Operands: None Operation: (PC) + 1 Top of Stack; k PC<7:0>; (STATUS<6:5>) PC<10:9>; 0 PC<8> Operation: 00h (W); 1Z Status Affected: None Encoding: Description: 1001 kkkk kkkk Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>.
PIC16C505 COMF Complement f Syntax: [ label ] COMF DECFSZ Decrement f, Skip if 0 Syntax: [ label ] DECFSZ f,d Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) (dest) Operation: (f) – 1 d; f,d Status Affected: Z Encoding: Description: 0010 01df ffff The contents of register 'f' are complemented. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
PIC16C505 INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: (f) + 1 (dest) Operation: (f) + 1 (dest), skip if result = 0 INCF f,d Status Affected: Z Encoding: Description: Status Affected: None 0010 10df ffff The contents of register 'f' are incremented. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
PIC16C505 IORLW Inclusive OR literal with W MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (W) .OR. (k) (W) 0 f 31 d [0,1] Status Affected: Z Operation: (f) (dest) Encoding: Status Affected: Z IORLW k 1101 Description: kkkk kkkk The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register.
PIC16C505 MOVWF Move W to f Syntax: [ label ] Operands: 0 f 31 Operands: None (W) (f) Operation: (W) OPTION Operation: MOVWF f 0000 Load OPTION Register Syntax: [ label ] 001f ffff Description: Move data from the W register to register 'f'.
PIC16C505 RLF Rotate Left f through Carry RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 31 d [0,1] Operands: 0 f 31 d [0,1] Operation: See description below Operation: See description below RLF f,d Status Affected: C Encoding: Description: Status Affected: C 0011 01df C 1 Cycles: 1 Example: RLF = = REG1,0 DS40192D-page 48 = = = Description: 0011 00df ffff The contents of register 'f' are rotated one bit to the right through t
PIC16C505 SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] Syntax: [label] Operands: None Operands: Operation: 00h WDT; 0 WDT prescaler; 1 TO; 0 PD 0 f 31 d [0,1] Operation: (f) – (W) dest) SLEEP Status Affected: TO, PD, RBWUF Encoding: Description: 0000 0000 Words: 1 Cycles: 1 Example: SLEEP Status Affected: C, DC, Z Encoding: 0000 10df ffff Description: Subtract (2’s complement method) the W register from register 'f'.
PIC16C505 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 f 31 d [0,1] Operands: 0 k 255 (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) Operation: (W) .XOR. k W) Status Affected: Z Operation: Encoding: Status Affected: None Encoding: Description: 0011 10df ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W register.
PIC16C505 9.
PIC16C505 9.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 9.
PIC16C505 9.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16C505 9.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16C505 10.0 ELECTRICAL CHARACTERISTICS - PIC16C505 Absolute Maximum Ratings† Ambient Temperature under bias ........................................................................................................... –40°C to +125°C Storage Temperature ............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS ..............................................................................
PIC16C505 FIGURE 10-1: PIC16C505 VOLTAGE-FREQUENCY GRAPH, 0C TA +70C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16C505 FIGURE 10-3: PIC16LC505 VOLTAGE-FREQUENCY GRAPH, -40C TA +85C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 20 25 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency. Please reference the Product Identification System section for the maximum rated speed of the parts. 1999-2012 Microchip Technology Inc.
PIC16C505 10.1 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) –40C TA +85C (industrial) –40C TA +125C (extended) DC Characteristics Power Supply Pins Parm. No. Characteristic Sym Min Typ(1) Max Units Conditions D001 Supply Voltage VDD 3.0 5.
PIC16C505 10.2 DC CHARACTERISTICS: PIC16LC505-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) –40C TA +85C (industrial) DC Characteristics Power Supply Pins Parm. No. Characteristic Sym Min Typ(1) Max Units Conditions D001 Supply Voltage VDD 2.5 — 5.5 V See Figure 10-1 through Figure 10-3 D002 RAM Data Retention Voltage(2) VDR — 1.
PIC16C505 10.3 DC CHARACTERISTICS: DC CHARACTERISTICS Param No.
PIC16C505 DC CHARACTERISTICS Param No. Characteristic Output High Voltage I/O ports/CLKOUT (Note 3) D090 Standard Operating Conditions (unless otherwise specified) Operating temperature 0°C TA +70°C (commercial) –40°C TA +85°C (industrial) –40°C TA +125°C (extended) Operating voltage VDD range as described in DC spec Section 10.1 and Section 10.3. Sym Min Typ† Max Units Conditions VOH VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.7 — — V VDD - 0.
PIC16C505 TABLE 10-1: VDD (Volts) PULL-UP RESISTOR RANGES - PIC16C505 Temperature (C) Min –40 25 85 125 –40 25 85 125 38K 42K 42K 50K 15K 18K 19K 22K –40 25 85 125 –40 25 85 125 285K 343K 368K 431K 247K 288K 306K 351K Typ Max Units 42K 48K 49K 55K 17K 20K 22K 24K 63K 63K 63K 63K 20K 23K 25K 28K W W W W W W W W 346K 414K 457K 504K 292K 341K 371K 407K 417K 532K 532K 593K 360K 437K 448K 500K W W W W W W W W RB0/RB1/RB4 2.5 5.5 RB3 2.5 5.
PIC16C505 10.4 Timing Parameter Symbology and Load Conditions - PIC16C505 The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16C505 10.5 Timing Diagrams and Specifications FIGURE 10-5: EXTERNAL CLOCK TIMING - PIC16C505 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 AC Characteristics Parameter No. 1A Sym FOSC Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), –40C TA +85C (industrial), –40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.
PIC16C505 TABLE 10-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED) AC Characteristics Parameter No. 3 Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial), –40C TA +85C (industrial), –40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.
PIC16C505 FIGURE 10-6: I/O TIMING - PIC16C505 Q1 Q4 Q2 Q3 OSC1 I/O Pin (input) 17 I/O Pin (output) 19 18 New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT. TABLE 10-4: TIMING REQUIREMENTS - PIC16C505 AC Characteristics Parameter No.
PIC16C505 FIGURE 10-7: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505 VDD MCLR 30 Internal POR 32 32 32 DRT Timeout (Note 2) Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT, LP and HS modes.
PIC16C505 FIGURE 10-8: TIMER0 CLOCK TIMINGS - PIC16C505 T0CKI 40 41 42 TABLE 10-7: TIMER0 CLOCK REQUIREMENTS - PIC16C505 AC Characteristics Parm Sym No. 40 Tt0H Standard Operating Conditions (unless otherwise specified) Operating Temperature 0C TA +70C (commercial) –40C TA +85C (industrial) –40C TA +125C (extended) Operating Voltage VDD range is described in Section 10.1.
PIC16C505 DC AND AC CHARACTERISTICS PIC16C505 The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
PIC16C505 TABLE 11-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C Oscillator External RC Internal RC XT LP HS Note 1: 2: Frequency VDD = 3.0V(1) VDD = 5.5V 4 MHz 4 MHz 4 MHz 32 kHz 20 MHz 240 µA(2) 320 µA 300 µA 19 µA N/A 800 µA(2) 800 µA 800 µA 50 µA 4.5 mA LP oscillator based on VDD = 2.5V Does not include current through external R&C. FIGURE 11-3: WDT TIMER TIME-OUT PERIOD vs. VDD FIGURE 11-4: SHORT DRT PERIOD VS.
PIC16C505 FIGURE 11-5: IOH vs. VOH, VDD = 2.5 V FIGURE 11-7: IOL vs. VOL, VDD = 2.5 V 25 0 -1 20 Max –40C 15 -3 IOL (mA) IOH (mA) -2 -4 10 125C Min + -5 8 Min + -6 Typ +25C Min +85C 5C Min +125C 5 Typ +25C C Max –40 -7 500m 1.0 1.5 2.0 2.5 0 VOH (Volts) 0 250.0m 500.0m 1.0 VOL (Volts) FIGURE 11-6: IOH vs. VOH, VDD = 5.5 V FIGURE 11-8: IOL vs. VOL, VDD = 5.
PIC16C505 NOTES: DS40192D-page 72 1999-2012 Microchip Technology Inc.
PIC16C505 12.0 PACKAGING INFORMATION 12.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16C505 -04/P e3 9904SAZ 14-Lead SOIC (3.90 mm) Example PIC16C505 -04/SL e3 9904SAZ 14-Lead TSSOP (4.4 mm) XXXXXXXX XXXYYWW YYWW NNN NNN Legend: XX...
PIC16C505 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6 % & 9 & % 7!&( $ 7+8- 7 7 % ; % % 7: 1 + < < 0 , 0 1 % % 0 < < - , , 0 " " 4 ! " % 4 ! " = "% " "
PIC16C505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2012 Microchip Technology Inc.
PIC16C505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40192D-page 76 1999-2012 Microchip Technology Inc.
PIC16C505 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 1999-2012 Microchip Technology Inc.
PIC16C505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40192D-page 78 1999-2012 Microchip Technology Inc.
PIC16C505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2012 Microchip Technology Inc.
PIC16C505 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40192D-page 80 1999-2012 Microchip Technology Inc.
PIC18F66K80 FAMILY APPENDIX A: REVISION HISTORY Revision D (June 2012) • Section 12.0 “Packaging Information” was updated with current package outline drawings. • Removed Section 2.1 “UV Erasable Devices” section. 1999-2012 Microchip Technology Inc.
PIC18F66K80 FAMILY NOTES: DS40192D-page 82 1999-2012 Microchip Technology Inc.
PIC16C505 INDEX A L ALU ....................................................................................... 7 Applications........................................................................... 3 Architectural Overview .......................................................... 7 Assembler MPASM Assembler..................................................... 52 M B Block Diagram On-Chip Reset Circuit ................................................. 33 Timer0.......................................
PIC16C505 W Wake-up from SLEEP ......................................................... 37 Watchdog Timer (WDT) ................................................ 27, 34 Period.......................................................................... 35 Programming Considerations ..................................... 35 WWW Address.................................................................... 85 WWW, On-Line Support........................................................ 2 Z Zero bit .................
PIC16C505 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16C505 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16C505 PIC16C505 Product Identification System Examples PART NO. -XX X /XX XXX Pattern: Special Requirements Package: SL P ST = 150 mil SOIC = 300 mil PDIP = 4.4 mm TSSOP Temperature Range: I E = 0C to +70C = -40C to +85C = -40C to +125C Frequency Range: 04 20 = 4 MHz (XT, INTRC, EXTRC OSC) = 20 MHz (HS OSC) Device PIC16C505 PIC16LC505 PIC16C505T (Tape & reel for SOIC only) PIC16LC505T (Tape & reel for SOIC only) a) PIC16C505-04/P Commercial Temp.
PIC16C505 NOTES: DS40192D-page 88 1999-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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