Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 85
PIC14000
10.7 Watchdog Timer (WDT)
The watchdog timer is realized as a free running
on-chip RC oscillator which does not require any
external components. This RC oscillator is separate
from the IN oscillator used to generate the CPU and
A/D clocks. That means that the WDT will run even if
the clock has been stopped, for example, by execution
of a SLEEP instruction. Refer to Section 10.8.1 for more
information.
During normal operation, a WDT time-out generates a
device RESET. If the device is in SLEEP mode, a WDT
time-out causes the device to wake-up and continue
with normal operation.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a ‘0’. Its
oscillator can be shut down to conserve battery power
by entering HIBERNATE Mode. Refer to
Section 10.8.3 for more information on HIBERNATE
mode.
A block diagram of the watchdog timer is shown in
Figure 10-11. It should be noted that a RESET
generated by the WDT time-out does not drive MCLR
low.
CAUTION: Beware of disabling WDT if software
routines require exiting based on WDT
reset. For example, the MCU will not
exit HIBERNATE mode based on WDT
reset.
FIGURE 10-11: WATCHDOG TIMER BLOCK DIAGRAM (WITH TIMER0)
RC3/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Sync with
Internal
clocks
TMR0
PSout
(2 cycle delay)
PSout
Data bus
8
PSA
Set T0IF
Interrupt on
Overflow
8-bit Counter
8-to-1 MUX
18 mS
Timer
PSA
01
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 correspond to (OPTION<5:0>).
PSA
0
1
3
HIBERNATE
WDT
Enable Bit
Local
Oscillator
Prescaler/
Postscaler
Enable
Watchdog Timer
Timer0