Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 83
PIC14000
10.6.1 EXTERNAL INTERRUPT
An external interrupt can be generated via the
OSC1/PBTN pin if IN (internal oscillator) mode is
enabled. This interrupt is falling edge triggered. When
a valid edge appears on OSC1/PBTN pin, PBIF
(PIR1<4>) is set. This interrupt can be disabled by
clearing PBIE (PIE1<4>). PBIF must be cleared in soft-
ware in the interrupt service routine before re-enabling
the interrupt. This interrupt can wake up the processor
from SLEEP if PBIE bit is set (interrupt enabled) prior
to going into SLEEP mode. The status of the GIE bit
determines whether or not the processor branches to
the interrupt vector following wake-up. The timing of the
external interrupt is shown in Figure 10-10.
FIGURE 10-10: EXTERNAL (OSC1/PBTN) INTERRUPT TIMING
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
INTERNAL
CLKOUT(3)
PBTN pin
PBIF flag
(PIR<4>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Interrupt Latency
PC PC+1 PC+1 0004h 0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC+1)
Inst (PC-1) Inst (0004h)Dummy CycleInst (PC)
—
1
4
5
1
Notes:
1. PBIF flag is sampled here (every Q1)
2. Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3. Available only in IN oscillator mode on OSC2.
4. For minimum width spec of PBTN pulse, refer to AC specs.
5. PBIF is enabled to be set anytime during the Q4-Q1 cycles.
(Note 2)
OSC