Datasheet

 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 81
PIC14000
TABLE 10-5: RESET CONDITIONS FOR REGISTERS
Register Address Power-on Reset
MCLR reset during
- normal operation
- SLEEP
WDT time-out during
normal operation
Wake-up from SLEEP
through interrupt
Wake up from SLEEP
through WDT time-out
W- xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h -- -
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h 0000h 0000h PC + 1
(2)
STATUS 03h/83h 0001 1xxx 000? ?uuu
(3)
uuu? ?uuu
(3)
FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---- xxxx ---- uuuu ---- uuuu
PORTC 07h xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 08h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh 0000 000x 0000 000u uuuu uuuu
(1)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu
(1)
ADTMRL 0Eh 0000 0000 0000 0000 uuuu uuuu
ADTMRH 0Fh 0000 0000 0000 0000 uuuu uuuu
I2CBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu
I2CCON 14h 0000 0000 0000 0000 uuuu uuuu
ADCAPL 15h 0000 0000 0000 0000 uuuu uuuu
ADCAPH 16h 0000 0000 0000 0000 uuuu uuuu
ADCON0 1Fh 0000 0010 0000 0010 uuuu uuuu
OPTION 81h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h ---- 1111 ---- 1111 ---- uuuu
TRISC 87h 1111 1111 1111 1111 uuuu uuuu
TRISD 88h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh ---- --0x ---- --uu ---- --uu
SLPCON 8Fh 0011 1111 0011 1111 uuuu uuuu
I2CADD 93h 0000 0000 0000 0000 uuuu uuuu
I2CSTAT 94h --00 0000 --00 0000 --uu uuuu
PREFA 9Bh 0000 0000 0000 0000 uuuu uuuu
PREFB 9Ch 0000 0000 0000 0000 uuuu uuuu
CMCON 9Dh 0x00 0x00 0x00 0x00 uuuu uuuu
MISC 9Eh 0000 000x 0000 000x uuuu uuuu
ADCON1 9Fh 0000 0000 0000 0000 uuuu uuuu
Legend: u=unchanged, x =unknown, - = unimplemented, reads as ‘0’, ? = value depends on condition.
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 10-4 for reset value for specific condition.