Datasheet

PIC14000
DS40122B-page 80
Preliminary
 1996 Microchip Technology Inc.
10.5.5 TIMEOUT SEQUENCE
On power-up the time-out sequence is as follows: First
the PWRT time-out is invoked after POR
has expired.
The OST is activated only in HS (crystal oscillator)
mode. The total time-out will vary based on the oscilla-
tor configuration and PWR
TE status. For example, in
IN mode, with PWR
TE unprogrammed (PWRT dis-
abled), there will be no time-out delay at all.
Figure 13-4 depicts the power-on reset time-out
sequences.
Table 10-4 shows the reset conditions for some special
registers, while Table 10-5 shows the reset conditions
for all registers.
FIGURE 10-8: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
V
DD
POWER-UP)
1. External power-on reset circuit is required
only if V
DD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when V
DD powers down.
2. R < 40 KΩ is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 µA). A larger voltage drop will
degrade VIH level on MCLR
pin.
3. R1 = 100 Ω to 1 KΩ will limit any current
flowing into MCLR
from external capacitor C
in the event of MCLR
pin breakdown due to
ESD or EOS.
PIC14000
MCLR
VDD
D
C
R1
R
VDD
TABLE 10-4: RESET CONDITION FOR SPECIAL REGISTERS
Legend: u = unchanged
x = unknown
- = unimplemented, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
Condition
PCL
Addr: 02h
STATUS
Addr: 03h
PCON
Addr: 8Eh
Power-on Reset
000h 0001 1xxx 0--- --0x
MCLR
reset during normal operation
000h 0001 1uuu u--- --ux
MCLR
reset during SLEEP
000h 0001 0uuu u--- --ux
WDT reset during normal operation
000h 0000 1uuu u--- --ux
WDT during SLEEP
PC + 1 uuu0 0uuu u--- --ux
Interrupt wake-up from SLEEP
PC + 1
(1)
uuu1 0uuu u--- --ux