Datasheet

PIC14000
DS40122B-page 58
Preliminary
 1996 Microchip Technology Inc.
Caution: Reading or writing the ADTMR register
during an A/D conversion cycle can pro-
duce unpredictable results and is not
recommended.
During conversion one or both of the following events
will occur:
1. capture event
2. timer overflow
In a capture event, the comparator trips when the slope
voltage on the CDAC output exceeds the input voltage,
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
Note: The correct sequence for writing the
ADTMR register is HI byte followed by LO
byte. Reversing this order will prevent the
A/D timer from running.
A CPU interrupt will be generated if bit ADCIE
(PIE1<1>) is set to ‘1’ (interrupt enabled). In addition,
the Global Interrupt Enable and Peripheral Interrupt
Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
conversion cycle. Note that this interrupt can only occur
once per conversion cycle.
In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
is asserted (PIR1<0>). The timer continues to incre-
ment following a timer overflow. A CPU interrupt can be
generated if bit OVFIE (PIE1<0>) is set (interrupt
enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
be set. Software is responsible for clearing the OVFIF
flag prior to the next conversion cycle.
FIGURE 8-1: A/D BLOCK DIAGRAM
(nominal)
ADOFF
WRITE_TMR
OSC1
1
0
FOSC
(Configuration Bit)
Internal
ADTMRH ADTMRL
Clock
Stop
Logic
Timer
(OVFIF, PIR1<0>)
ADCAPH ADCAPL
Oscillator
Analog
Mux
Prog. Ref. A
7
6
5
4
3
2
1
0
Temp sensor
SREFLO
SREFHI
RA2/AN2
RA1/AN1
RA0/AN0
A/D Capture
A/D
Capture Interrupt
ADOFF
CDAC
~2.5uA~5uA~10uA~20uA
ADCON1<7:4>
0.1µF
ADRST (ADCON0<1>)
RA3/AN3
8
~100 Ω
ADOFF
Bandgap Ref.
Prog. Ref. B
9
~ 1 kohm
RD4/AN4
RD5/AN5
RD6/AN6
RD7/AN7
10
11
12
13
RESERVED
RESERVED
14
15
AMUXOE
(ADCIF, PIR1<1>)
Overflow
Internal
Data
Bus
ADRST
4
Note 2
Note 1: All current sources are disabled if ADRST = ‘1’
Note 2: Approximately 3.5 microsecond time constant
Note 1
4-Bit Current DAC
ADCON0<7:4>
(SLPCON<0>)
(ADCON0<2>)
RA0/AN0