Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 55
PIC14000
7.5.4 SMBus AND ACCESS.bus
CONSIDERATIONS
PIC14000 is compliant with the SMBus specification
published by Intel. Some key points to note regarding
the bus specifications and how it pertains to the
PIC14000 hardware are listed below:
• SMBus has fixed input voltage thresholds.
PIC14000 I/O buffers have programmable levels
that can be selected to be compatible with both
SMBus threshold levels via the SMBus and
SPGND bits in the MISC register.
• A mechanism to stretch the I
2
C clock time has
been implemented to support SMBus slave
transactions. The SMHOG bit (MISC<7>) allows
hardware to automatically force and hold the I
2
C
clock line low when a data byte has been
received. This prevents the SMBus master from
overflowing the receive buffer in instances where
the microcontroller may be to busy servicing
higher priority tasks to respond to a I
2
C module
interrupt. Or, if the microcontroller is in SLEEP
mode and needs time to wake-up and respond to
the I
2
C interrupt.
FIGURE 7-18: SMHOG STATE MACHINE
SMHOG = 0
SMHOG = 1
I
2
CIF = 1
SMHOG = 0
SMHOG = 0
SMHOG = 0
SMHOG = 0
I
2
CIF = 0
I
2
CIF = 0
I
2
CIF = 1
I
2
CIF = 0
I
2
CIF = 0
I
2
CIF = 1
SCL = 0
SCL = 1
A
B
C
D
E/DRIVE
SCL
LOW