Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 51
PIC14000
7.5.1.3 TRANSMISSION
When the R/W
bit of the address byte is set and an
address match occurs, the R/W
bit of the I
2
CSTAT
register is set. The received address is loaded into the
I
2
CBUF The ACK pulse will be sent on the ninth bit, and
the SCL pin is held low. The transmit data must be
loaded into the I
2
CBUF register, which also loads the
I
2
CSR register. Then the SCL pin should be enabled by
setting the CKP bit (I
2
CCON<4>). The eight data bits
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 7-15).
A I
2
CIF interrupt is generated for each data transfer
byte. The I
2
CIF bit must be cleared in software, and the
I
2
CSTAT register is used to determine the status of the
byte. The I
2
CIF bit is set on the falling edge of the ninth
clock pulse.
As a slave-transmitter, the ACK
pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK
), then the data transfer is complete. The slave
then monitors for another occurrence of the START bit.
If the SDA line was low (ACK
), the transmit data must
be loaded into the I
2
CBUF register, which also loads
the I
2
CSR register. Then the SCL pin should be
enabled by setting the CKP bit (I
2
CCON<4>).
FIGURE 7-15: I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
I
2
CIF (PIR1<3>)
BF (I
2
CSTAT<0>)
CKP (I
2
CCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Transmitting DataR/W = 1Receiving Address
123456789 123456789
P
cleared in software
I
2
CBUF is written in software
From I
2
CIF interrupt
service routine
Set bit after writing to I
2
CBUF
S
Data in
sampled
SCL held low
while CPU
responds to I
2
CIF