Datasheet

PIC14000
DS40122B-page 50 Preliminary  1996 Microchip Technology Inc.
7.5.1.1 ADDRESSING
Once the I
2
C module has been enabled, the I
2
C waits
for a START to occur. Following the START, the 8-bits
are shifted into the I
2
CSR. All incoming bits are
sampled with the rising edge of the clock (SCL) line.
The I
2
CSR<7:1> is compared to the I
2
CADD register.
The address is compared on the falling edge of the
eighth clock (SCL) pulse. If the addresses match, and
the BF and I
2
COV bits are clear, the following things
happen:
• I
2
CSR loaded into I
2
CBUF
• Buffer Full (BF) bit is set
• ACK
pulse is generated
• I
2
C Interrupt Flag (I
2
CIF) is set (interrupt is
generated if enabled (I
2
CIE set) on falling edge of
ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 7-5). The five most
significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. The R/W
bit (bit 0) must
specify a write, so the slave device will received the
second address byte. For a 10-bit address the first byte
would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7-9 for
slave-transmitter:
1. Receive first (high) byte of address (I
2
CIF, BF
and UA are set).
2. Update I
2
CADD with second (low) byte of
address (clears UA and releases SCL line).
3. Read I
2
CBUF (clears BF) and clear I
2
CIF.
4. Receive second (low) byte of address (I
2
CIF, BF
and UA are set).
5. Update I
2
CADD with first (high) byte of address
(clears UA, if match releases SCL line).
6. Read I
2
CBUF (clears BF) and clear I
2
CIF
7. Receive Repeated START.
8. Receive first (high) byte of address (I
2
CIF and
BF are set).
9. Read I
2
CBUF (clears BF) and clear I
2
CIF.
7.5.1.2 RECEPTION
When the R/W
bit of the address byte is clear and an
address match occurs, the R/W
bit of the I
2
CSTAT
register is cleared. The received address is loaded into
the I
2
CBUF.
When the address byte overflow condition exists then
no acknowledge (ACK
) pulse is given. An overflow
condition is defined as either the BF bit (I
2
CSTAT<0>)
is set or the I
2
COV bit (I
2
CCON<6>) is set
(Figure 7-14).
An I
2
CIF interrupt is generated for each data transfer
byte. The I
2
CIF bit must be cleared in software, and the
I
2
CSTAT register is used to determine the status of the
byte. In master mode with slave enabled, three inter-
rupt sources are possible. Reading BF, P and S will
indicate the source of the interrupt.
Caution: BF is set after receipt of eight bits and auto-
matically cleared after the I
2
CBUF is read.
However, the flag is not actually cleared
until receipt of the acknowledge pulse. Oth-
erwise extra reads appear to be valid.
FIGURE 7-14: I
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
123
4
Bus Master
terminates
transfer
I
2
COV is set
because I
2
CBUF is
Cleared in software
I
2
CBUF is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4
D5
D6D7
ACK
Receiving Address
I
2
CIF (PIR1<3>)
BF (I
2
CSTAT<0>)
I
2
COV (I
2
CCON<6>)
ACK
R/W=0
still full. ACK
is not sent.