Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 49
PIC14000
7.5.1 SLAVE MODE
In slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<7:6> or TRISD<1:0> are
set). The I
2
C module will override the input state with
the output data when required (slave-transmitter).
When an address is matched or the data transfer from
an address match is received, the hardware
automatically will generate the acknowledge (ACK
)
pulse, and then load the I
2
CBUF with the received
value in the I
2
CSR.
There are two conditions that will cause the I
2
C module
not to give this ACK
pulse. These are if either (or both)
occur:
• the Buffer Full (BF), I
2
CSTAT<0>, bit was set
before the transfer was received, or
• the Overflow (I
2
COV), I
2
CCON<6> bit was set
before the transfer was received.
In this case, the I
2
CSR value is not loaded into the
I
2
CBUF, but the I
2
CIF bit is set. Table 7-2 shows what
happens when a data transfer byte is received, given
the status of the BF and I
2
COV bits. The shaded boxes
show the conditions where user software did not
properly clear the overflow condition. The BF flag is
cleared by reading the I
2
CBUF register while the
I
2
COV bit is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
2
C specification as well as the requirement of the I
2
C
module is shown in the AC timing specifications.
TABLE 7-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data Transfer
is Received
BF I
2
COV I
2
CSR-> I
2
CBUF
Generate A
CK Pulse
Set I
2
CIF bit
(I
2
C interrupt if enabled)
0 0 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 No No Yes