Datasheet

PIC14000
DS40122B-page 48
Preliminary
 1996 Microchip Technology Inc.
FIGURE 7-13: I
2
C BLOCK DIAGRAM
Read Write
Internal
data bus
RC7/SDAA
I
2
CSR
I
2
CBUF
MSB
Match Detect
Start and
RC6/SCLA
I
2
CADD
Stop bit detect
Addr_Match
Set, Reset
S, P bits
(I
2
CSTAT Reg)
Shift
clock
RD1/SDAB
RD0/SCLB
4:2
MUX
SCK
SDA
MISC<4>
7.5 I
2
C Operation
The I
2
C module in I
2
C mode fully implements all slave
functions, and provides support in hardware to facilitate
software implementations of the master functions. The
I
2
C module implements the standard and fast mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/SCLA pin, which is the I
2
C clock, and the
RC7/SDAA pin which acts as the I
2
C data. The I
2
C
module can also be accessed via the RD0/SCLB and
RD1/SDAB pins by setting I
2
CSEL (MISC<4>).The
user must configure these pins as inputs or outputs
through the TRISC<7:6> or TRISD<1:0> bits. A block
diagram of the I
2
C module in I
2
C mode is shown in
Figure 7-13. The I
2
C module functions are enabled by
setting the I
2
CCON<5> bit.
The I
2
C module has five registers for I
2
C operation.
These are the:
•I
2
C Control Register (I
2
CCON)
•I
2
C Status Register (I
2
CSTAT)
• Serial Receive/Transmit Buffer (I
2
CBUF)
•I
2
C Shift Register (I
2
CSR) - Not directly
accessible
• Address Register (I
2
CADD)
The I
2
CCON register (14h) allows control of the I
2
C
operation. Four mode selection bits (I
2
CCON<3:0>)
allow one of the following I
2
C modes to be selected:
•I
2
C Slave mode (7-bit address)
•I
2
C Slave mode (10-bit address)
•I
2
C Slave mode (7-bit address), with start and
stop bit interrupts enabled
•I
2
C Slave mode (10-bit address), with start and
stop bit interrupts enabled
•I
2
C Firmware Controlled Master mode, slave is
idle
Selection of any I
2
C mode with the I
2
CEN bit set, forces
the SCL and SDA pins to be open collector, provided
these pins are set to inputs through the TRISC bits.
The I
2
CSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The I
2
CSTAT register is read only.
The I
2
CBUF is the register to which transfer data is
written to or read from. The I
2
CSR register shifts the
data in or out of the device. In receive operations, the
I
2
CBUF and I
2
CSR create a double buffered receiver.
This allows reception of the next byte before reading
the last byte of received data. When the complete byte
is received, it is transferred to the I
2
CBUF and PIR1<3>
is set. If another complete byte is received before the
I
2
CBUF is read, a receiver overflow has occurred and
the I
2
CCON<6> is set.
The I
2
CADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1 1 1 1 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7-A0).