Datasheet

 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 47
PIC14000
7.4 Multi-Master Operation
The I
2
C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
7.4.1 ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 7-11) and turns off its data output stage. A
master which lost arbitrating can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning
master-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START
• A STOP and a data bit
• A repeated START and a STOP
Care needs to be taken to ensure that these conditions
do not occur.
7.4.2 CLOCK SYNCHRONIZATION
Clock synchronization occurs after the devices have
started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high
transition of this clock may not change the state of the
SCL line, if another device clock is still within its low
period. The SCL line is held low by the device with the
longest low period. Devices with shorter low periods
enter a high wait-state, until the SCL line comes high.
When the SCL line comes high, all devices start
counting off their high periods. The first device to
complete its high period will pull the SCL line low. The
SCA line high time is determined by the device with the
shortest high period. This is shown in the Figure 7-12.
FIGURE 7-11: MULTI-MASTER
ARBITRATION (2 MASTERS)
FIGURE 7-12: I
2
C CLOCK
SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1≠ SDA
DATA 1
DATA 2
SDA
SCL
wait
state
start counting
HIGH period
CLK
1
CLK
2
SCL
counter
reset