Datasheet

PIC14000
DS40122B-page 44
Preliminary
 1996 Microchip Technology Inc.
TABLE 7-1: I
2
C BUS TERMINOLOGY
Term Description
Transmitter The device that sends the data to the bus.
Receiver The device that receives the data from the bus.
Master The device which initiates the transfer, generates the clock, and terminates the transfer.
Slave The device addressed by a master.
Multi-master More than one master device in a system. These masters can attempt to control the bus
at the same time without corrupting the message.
Arbitration Procedure that ensures that only one of the master devices will control the bus. This
ensures that the transfer data does not get corrupted.
Synchronization Procedure where the clock signals of two or more devices are synchronized.
FIGURE 7-4: I
2
C 7-BIT ADDRESS FORMAT
FIGURE 7-5: I
2
C 10-BIT ADDRESS
FORMAT
S
R/W
ACK
Sent by
Slave
slave address
S
R/W
Read/Write pulse
MSb LSb
Start Condition
ACK
Acknowledge
sent by slave
= 0 for write
S1
S
R/W
ACK
1 1 1 0 A9 A8 RW ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
-
-
-
Start Condition
Read/Write Pulse
Acknowledge
7.2 Ad
dressing I
2
C De
vices
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 7-4). The
address is the most significant seven bits of the byte.
For example when loading the I
2
CADD register, the
least significant bit is a “don’t care”. The more complex
is the 10-bit address with a R/W
bit (Figure 7-5). For
10-bit address format, two bytes must be transmitted
with the first five bits specifying this to be a 10-bit
address.