Datasheet

 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 39
PIC14000
6.2 Using
Timer0 with External Clock
When the external clock input (pin RC3/T0CKI) is used
for Timer0, it must meet certain requirements. The
external clock requirement is due to internal phase
clock (T
OSC ) synchronization. Also, there is a delay in
the actual incrementing of TMR0 after synchronization.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (and a small RC delay of 20 ns)
and low for at least 2Tosc (and a small RC delay of
20 ns).
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns.
6.2.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
6.3 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a post-scaler for the Watchdog
Timer (Figure 6-1). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
Bit PSA and PS2:PS0 (OPTION<3:0>) determine the
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the Timer0 module (e.g., CLRF 1, MOVWF 1,
BSF 1,x ) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
INCREMENT TMR0 (Q4)
EXT CLOCK INPUT OR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TMR0
T0 T0 + 1 T0 + 2
Small pulse
misses sampling
EXT CLOCK/PRESCALER
OUTPUT AFTER SAMPLING
(note 3)
1.
2.
3.
Delay from clock input change to TMR0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4 tosc max.
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.
Notes:
PRESCALER OUT (NOTE 2)