Datasheet

PIC14000
DS40122B-page 26
Preliminary
 1996 Microchip Technology Inc.
FIGURE 5-2: PORTA DATA REGISTER
05h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTA — — — — RA3/AN3 RA2/AN2 RA1/AN1 RA0/AN0
Read/Write U U U U R/W R/W R/W R/W
POR value 0xh 0000XXXX
Bit Name Function
B7-B4
—
Unimplemented. Reads as‘0’.
B3 RA3/AN3 GPIO or analog input. Returns value on pin RA3/AN3 when used as a digital
input. When configured as an analog input, reads as ‘0’.
B2 RA2/AN2 GPIO or analog input. Returns value on pin RA2/AN2 when used as a digital
input. When configured as an analog input, reads as ‘0’.
B1 RA1/AN1 GPIO or analog input. Returns value on RA1/AN1 when used as a digital input.
This pin can connect to a level shift network. If enabled, a +0.5V offset is added
to the input voltage. When configured as an analog input, reads as ‘0’.
B0 RA0/AN0 GPIO or analog input. Returns value on pin RA0/AN0 when used as a digital
input. When configured as an analog input, reads as ‘0’.
5.2 POR
TC and TRISC
PORTC is a 8-bit wide bidirectional port, with Schmitt
Trigger inputs, that serves the following functions
depending on programming:
• Direct LED drive (PORTC<7:0>).
•I
2
C communication lines (PORTC<7:6>), refer to
Section 7.0 I
2
C Serial Port.
• Interrupt on change function (PORTC<7:4>),
discussed below and in Section 10.3 Interrupts.
• Programmable reference and comparator
outputs.
• Timer0 clock source on RC3
The PORTC data register is located at location 07h and
its data direction register (TRISC) is at 87h.
PORTC<5:0> have weak internal pull-ups (~100 uA
typical). A single control bit can turn on all the pull-ups.
This is done by clearing bit RCPU
(OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on power-on reset and in hibernate mode.
When using PORTC<0> as an analog output
(CMCON<1> bit is set), the TRISC<0> bit should be
cleared to disable the weak pull-up on this pin. Refer to
Table 5-1.
Four of the PORTC pins, RC<7:4> have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur. In other words, any pin
RC<7:4> configured as an output is excluded from the
interrupt on change comparison. The input pins of
RC<7:4> are compared with the old value latched on
the last read of PORTC. The “mismatch” outputs of
RC<7:4> are OR’ed together to assert the RCIF flag
(PIR1 register<2>) and cause a CPU interrupt, if
enabled.
Note: If the I
2
C function is enabled,
(I
2
CCON<5>, address 14h), RC<7:6> are
automatically excluded from the
interrupt-on-change comparison.