Datasheet

PIC14000
DS40122B-page 22 Preliminary  1996 Microchip Technology Inc.
4.2.2.6 PCON REGISTER
The Power Control (PCON) register status contains
2 flag bits to allow differentiation between a Power-on
Reset, an external MCLR
reset, WDT reset, or low-volt-
age condition (Figure 4-8).
These bits are cleared on POR. The user must set
these bits following POR. On a subsequent reset if
POR is cleared, this is an indication that the reset was
due to a power-on reset condition.
Note: LVD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if L
VD is
cleared, indicating a low voltage condition
has occurred.
FIGURE 4-8: PCON REGISTER
bit7 bit0
LVD —
POR
LVD: Low Voltage Detect Flag
1 = A low-voltage detect condition has not occurred.
0 = A low-voltage detect condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
Reserved. Bit 7 is reserved. This bit should be
R/W R/W
R/W U U U U U
r — — —
—
W: Writable
R: Readable
U: Unimplemented,
read as ‘0’
Register: PCON
Address: 8Eh
POR value:
0000_000xb
POR: Power on Reset Flag
1 = A power on reset condition has not occurred.
0 = A power on reset condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
Reset must be due to some other source
(WDT, MCLR
).
programmed as ‘0’ .
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’