Datasheet

 1996 Microchip Technology Inc. Preliminary DS40122B-page 21
PIC14000
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts (Figure 4-7).
Note: These bits will be set by the specified
condition, even if the corresponding
Interrupt Enable bit is cleared (interrupt
disabled) or the GIE bit is cleared (all
interrupts disabled). Before enabling an
interrupt, the user may wish to clear the
corresponding interrupt flag, to ensure that
the program does not immediately branch
to the Peripheral Interrupt service routine.
FIGURE 4-7: PIR1 REGISTER
CMIF
R/W R R
R/W R/W R/W R/W R/W
bit0bit7
CMIF: Programmable Reference Comparator Interrupt Flag
1 =The comparator output has tripped. This is a
0 = The interrupt did not occur
Unimplemented. Read as ‘0’
W: Writable
R: Readable
U: Unimplemented,
read as ‘0’
Register: PIR1
Address: 0Ch
POR value: 00h
—
—
PBIF
I
2
CIF RCIF ADCIF
OVFIF
Unimplemented. Read as ‘0’
OVFIF: A/D counter Overflow Interrupt Flag
1 =An A/D counter overflow has occurred.
Must be cleared in software.
0 = An A/D counter overflow has not occurred
ADCIF: A/D Capture Interrupt Flag
1 =An A/D capture has occurred.
Must be cleared in software.
0 = An A/D capture has not occurred
RCIF: PORTC Interrupt on Change Flag
1 =At least one RC<7:4> input changed.
Must be cleared in software.
0 =None of the RC<7:4> inputs have changed
I
2
CIF: I
2
C Port Interrupt Flag
1 =A transmission/reception is completed.
Must be cleared in software.
0 =Waiting to transmit/receive
PBIF: External Pushbutton Interrupt Flag
1 =The external pushbutton interrupt has occurred
0 =The external pushbutton interrupt did not occur
on OSC1/PBTN. Note: This interrupt is not available
in HS mode.
level-sensitive interrupt.