Datasheet
1996 Microchip Technology Inc. Preliminary DS40122B-page 117
PIC14000
FIGURE 13-7: I
2
C BUS DATA TIMING
TABLE 13-8: I
2
C BUS DATA REQUIREMENTS
Parameter
No.
Sym Characteristic Min Max Units Conditions
100 T
HIGH Clock high time 100 kHz mode 4.0 — µs PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — µs PIC14000 must operate at a
minimum of 10 MHz
I
2
C Module 1.5 TCY —
101 T
LOW Clock low time 100 kHz mode 4.7 — µs PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — µs PIC14000 must operate at a
minimum of 10 MHz
I
2
C Module 1.5 TCY —
102 T
R SDA and SCL rise
time
100 kHz mode — 1000 ns
400 kHz mode 20+0.1 C
b
300 ns C
b
is specified to be from
10-400 pF
103 T
F SDA and SCL fall
time
100 kHz mode — 300 ns
400 kHz mode 20+0.1 C
b
300 ns C
b
is specified to be from
10-400 pF
90 T
SU:STA START condition
setup time
100 kHz mode 4.7 — µs Only relevant for repeated
START condition
400 kHz mode 0.6 — µs
91 T
HD:STA START condition hold
time
100 kHz mode 4.0 — µs After this period the first clock
pulse is generated
400 kHz mode 0.6 — µs
106 T
HD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107 T
SU:DAT Data input setup time 100 kHz mode 250 — ns Note 2
400 kHz mode 100 — ns
92 T
SU:STO STOP condition setup
time
100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109 T
AA Output valid from
clock
100 kHz mode — 3500 ns Note 1
400 kHz mode — — ns
110 T
BUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — µs
C
b
Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.
2: A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement
t
SU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line T
R max.+tSU:DAT=1000+250=1250 ns (according to the standard-mode I
2
C
bus specification) before the SCL line is released.
SCL
SDA
IN
SDA
OUT
80
93
90
91
92
82
100
99
99
81
96
97
90
91 92
100
101
103
106
107
109
109
110
102
Note: Refer to Figure 13-2 for load conditions