PIC14000 28-Pin Programmable Mixed Signal Controller Pin Diagram High-Performance RISC CPU: • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input • 4096 x 14 on-chip EPROM program memory • 192 x 8 general purpose registers (SRAM) • 6 internal and 5 external interrupt sources • 38 special function hardware registers • Eight-level hardware stack PDIP, SOIC, SSOP, Windowed CERDIP • Slope Analog-t
PIC14000 TABLE OF CONTENTS 1.0: General Description........................................................................................................................... 3 2.0: Device Varieties ................................................................................................................................ 5 3.0: Architectural Overview ...................................................................................................................... 7 4.0: Memory Organization ........
PIC14000 1.0 GENERAL DESCRIPTION The PIC14000 features include medium to high resolution A/D conversion (10 to 16 bits), temperature sensing, closed loop charge control, serial communication, and low power operation. The PIC14000 uses a RISC Harvard architecture CPU with separate 14-bit instruction and 8-bit data buses. A two-stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches, which require two cycles. A total of 35 instructions are available.
PIC14000 NOTES: DS40122B-page 4 Preliminary 1996 Microchip Technology Inc.
PIC14000 2.0 DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. The PIC14000 Product Selection System section at the end of this data sheet provides the devices options to be selected for your specific application and production requirements. When placing orders, please use the “PIC14000 Product Identification System” at the back of this data sheet to specify the correct part number. 2.
PIC14000 NOTES: DS40122B-page 6 Preliminary 1996 Microchip Technology Inc.
PIC14000 3.0 ARCHITECTURAL OVERVIEW The PIC14000 addresses 4K x 14 program memory. All program memory is internal. The PIC14000 can directly or indirectly address its register files or data memory. All special function registers including the program counter are mapped in the data memory. The PIC14000 has an orthogonal instruction set that makes it possible to carry out any operation on any register using any addressing mode.
PIC14000 FIGURE 3-1: PIC14000 BLOCK DIAGRAM 13 Program Memory Program Bus 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3 RAM File Registers 192 x 8 8 Level Stack (13-bit) 4K x 14 8 Data Bus Program Counter EPROM RAM Addr (1) 9 Addr MUX Instruction reg 7 Direct Addr 8 Indirect Addr FSR reg PORTC RC0/REFA RC1/CMPA RC2 RC3/T0CKI RC4 RC5 RC6/SCLA RC7/SDAA STATUS reg 8 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Low Voltage Detecto
PIC14000 TABLE 3-1: PIN DESCRIPTIONS Pin No.
PIC14000 TABLE 3-1: PIN DESCRIPTIONS (CONTINUED) Pin No. I/O RD3/REFB 3 I/O-PU AN/ST CMOS RD4/AN4 26 I/O AN/ST CMOS RD5/AN5 25 I/O AN/ST CMOS RD6/AN6 24 I/O AN/ST CMOS RD7/AN7 23 I/O AN/ST CMOS VREG 10 O — AN OSC1/PBTN 8 I-PU ST — OSC2/ CLKOUT MCLR/VPP 7 O — CMOS 14 I/PWR ST 9 20 PWR GND Pin Name VDD VSS Pin Type Input Output Description General purpose I/O or programmable reference B output. Analog input channel 4. This pin can also serve as a GPIO.
PIC14000 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (from OSC1 or the internal oscillator) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. The program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-2.
PIC14000 NOTES: DS40122B-page 12 Preliminary 1996 Microchip Technology Inc.
PIC14000 4.0 MEMORY ORGANIZATION 4.1.1 4.1 Program Memory Organization The calibration space is not used for instructions. This section stores constants and factors for the arithmetic calculations to calibrate the analog measurements. The PIC14000 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 4K x 14 (0000-0FFFh) are physically implemented. Accessing a location above the physically implemented address will cause a wraparound.
PIC14000 TABLE 4-2: CALIBRATION CONSTANT ADDRESSES 4.2.1 GENERAL PURPOSE REGISTER FILE The register file is accessed either directly, or indirectly through the file select register FSR (Section 4.4). Address Data 0FC0h KREF , exponent 0FC1h KREF , mantissa high byte 00h Indirect add.(*) Indirect addr.
PIC14000 4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. TABLE 4-3: Address The special registers are classified into two sets. Special registers associated with the “core” functions are described in this section. Those registers related to the operation of the peripheral features are described in the section specific to that peripheral.
PIC14000 TABLE 4-3: Address SPECIAL FUNCTION REGISTERS FOR THE PIC14000 (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank1 81h INDF Addressing this location uses contents of FSR to address data memory (not a physical regis(Indirect Adter).
PIC14000 4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC14000 4.2.2.2 OPTION REGISTER Note: The OPTION register (Address 81h) is a readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, TMR0, and the weak pull-ups on PORTC<5:0>. Bit 6 is reserved.
PIC14000 4.2.2.3 INTCON REGISTER Note: The INTCON Register is a readable and writable register which contains the various enable and flag bits for the Timer0 overflow and peripheral interrupts. Figure 4-5 shows the bits for the INTCON register. FIGURE 4-5: R/W GIE R/W PEIE The T0IF will be set by the specified condition even if the corresponding Interrupt Enable Bit is cleared (interrupt disabled) or the GIE bit is cleared (all interrupts disabled).
PIC14000 4.2.2.4 PIE1 REGISTER Note: This register contains the individual enable bits for the Peripheral interrupts including A/D capture event, I2C serial port, PORTC change and A/D capture timer overflow, and external push button. FIGURE 4-6: R/W CMIE INTCON<6> must be enabled to enable any interrupt in PIE1.
PIC14000 4.2.2.5 PIR1 REGISTER Note: This register contains the individual flag bits for the Peripheral interrupts (Figure 4-7). FIGURE 4-7: R/W CMIF R — These bits will be set by the specified condition, even if the corresponding Interrupt Enable bit is cleared (interrupt disabled) or the GIE bit is cleared (all interrupts disabled).
PIC14000 4.2.2.6 PCON REGISTER The Power Control (PCON) register status contains 2 flag bits to allow differentiation between a Power-on Reset, an external MCLR reset, WDT reset, or low-voltage condition (Figure 4-8). FIGURE 4-8: These bits are cleared on POR. The user must set these bits following POR. On a subsequent reset if POR is cleared, this is an indication that the reset was due to a power-on reset condition. Note: LVD is unknown on Power-on Reset.
PIC14000 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte, PCL, is a readable and writable register. The high byte of the PC (PCH) is not directly readable or writable. PCLATH is a holding register for PC<12:8> where contents are transferred to the upper byte of the program counter. When PC is loaded with a new value during a CALL, GOTO or a write to PCL, the high bits of PC are loaded from PCLATH as shown in Figure 4-9.
PIC14000 4.4 Indirect Addressing, INDF and FSR Registers EXAMPLE 4-2: The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. movlw movf clrf incf btfss goto NEXT Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the file select register (FSR). Reading INDF itself indirectly will produce 00h.
PIC14000 5.0 I/O PORTS Note: The PIC14000 has three ports, PORTA, PORTC and PORTD, described in the following paragraphs. Generally, PORTA is used as the analog input port. PORTC is used for general purpose I/O and for host communication. PORTD provides additional I/O lines. Four lines of PORTD may function as analog inputs. 5.1 On Reset, PORTA is configured as analog inputs The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs.
PIC14000 FIGURE 5-2: PORTA DATA REGISTER 05h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA — — — — RA3/AN3 RA2/AN2 RA1/AN1 RA0/AN0 Read/Write U U U U R/W R/W R/W R/W POR value 0xh 0 0 0 0 X X X X Bit Name Function B7-B4 — Unimplemented. Reads as‘0’. B3 RA3/AN3 GPIO or analog input. Returns value on pin RA3/AN3 when used as a digital input. When configured as an analog input, reads as ‘0’. B2 RA2/AN2 GPIO or analog input.
PIC14000 This interrupt can wake the device up from SLEEP. The user, in the interrupt service routine, can clear the interrupt in one of two ways: • Disable the interrupt by clearing the RCIE (PIE1<2>) bit • Read PORTC. This will end mismatch condition. Then, clear the RCIF (PIR1<2>) bit. A mismatch condition will continue to set the RCIF bit. Reading PORTC will end the mismatch condition, and allow the RCIF bit to be cleared.
PIC14000 TABLE 5-1: PORT RC0 PIN CONFIGURATION SUMMARY RC0 Pin Configuration TRISC<0> Digital Input (weak pull-up) 1 0 0 Digital Input (no pull-up) 1 1 0 Digital Output 0 X 0 Analog Output 0 X 1 FIGURE 5-4: RCPU CMAOE OPTION<7> CMCON<1> Comment Must clear TRISC<0> to disable pull-up when used as an analog output.
PIC14000 FIGURE 5-5: BLOCK DIAGRAM OF PORTC<3:0> PINS RCPU Data Bus Write PORTC VDD D P CK Q D Write TRISC Q I/O Pin Q CK Q HIBERNATE Schmitt Trigger Input Buffer Read TRISC Read PORTC Q D EN Read PORTC 1. 2. 3. I/O pins have protection diodes to VDD and VSS. Port Latch =‘1’ and TRISC =‘1’ enables weak pull-up if RCPU =‘0’ in OPTION register. If the CMAOE bit (CMCON<1>) is set to‘1’, RC0 becomes REFA, RC1 becomes CMPA, ignoring the PORTC<1:0> data and TRISC<1:0> register settings.
PIC14000 FIGURE 5-6: PORTC DATA REGISTER 07h PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RC7/SDAA RC6/SCLA RC5 RC4 RC3/T0CKI RC2 RC1/CMPA RC0/REFA R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Read/Write POR value xxh Bit Name Function RC7/SDAA Synchronous serial data I/O for I2C interface. Also is the serial programming data line. This pin can also serve as a general purpose I/O. If enabled, a change on this pin can cause a CPU interrupt.
PIC14000 5.2.1 TRISC PORTC DATA DIRECTION REGISTER This register defines each pin of PORTC as either an input or output under software control. A ‘1’ in each location configures the corresponding port pin as an input. This register resets to all ‘1’s, meaning all PORTC pins are initially inputs. The data register should be initialized prior to configuring the port as outputs.
PIC14000 5.3 PORTD and TRISD PORTD is an 8-bit port that may be used for general purpose I/O. Four pins can be configured as analog inputs. FIGURE 5-8: BLOCK DIAGRAM OF PORTD<7:4> PINS Data Bus Write PORTD VDD D P CK Q D Write TRISD Q I/O Pin N Q VSS CK Q Analog Input Mode Read TRISD Schmitt Trigger Input Buffer Q D EN Read PortD To A/D Converter Note: I/O pins have protection diodes to VDD and VSS.
PIC14000 FIGURE 5-10: BLOCK DIAGRAM OF PORTD<1:0> PINS I2CCON<5> Data Bus Write PORTD D Q N CK Q D Write TRISD VDD I/O Pin N Q VSS CK Q Read TRISD Schmitt Trigger Input Buffer Q D EN Read PortD Note: I/O pins have protection diodes to VDD and VSS. These pins do not have a P-channel pull-up.
PIC14000 FIGURE 5-12: TRISD REGISTER 88h TRISD Read/Write POR value FFh Bit Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Function B7 TRISD7 Control direction on pin RD7/AN7: 0 = pin is an output 1 = pin is an input B6 TRISD6 Control direction on pin RD6/AN6: 0 = pin is an output 1 = pin is an input B5 TRISD5 Control direction on pin RD5/AN5: 0 = pin is an
PIC14000 If the CMBOE bit (CMCON<5>) is set, the RD3/REFB pin becomes the programmable reference B output and pin RD2/CMPB becomes the comparator B output. Note: Setting CMBOE changes the definition of RD3/REFB and RD2/CMPB, bypassing the PORTD data and TRISD register settings. PORTD<1:0> also serve multiple functions. These pins act as the I2C data and clock lines when the I2C module is enabled. The TRISD register controls the direction of the Port D pins.
PIC14000 5.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle. Therefore, care must be exercised if a write operation is followed by a read operation on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize before the next instruction which causes that port to be read into the CPU is executed.
PIC14000 6.0 TIMER MODULES • • • • The PIC14000 contains two general purpose timer modules, Timer0 (TMR0) and the Watchdog Timer (WDT). The ADTMR is described in the A/D section. 8-bit timer Readable and writable (file address 01h) 8-bit software programmable prescaler Interrupt on overflow from FFh to 00h Figure 6-1 is a simplified block diagram of the Timer0 module. The Timer0 module is identical to the Timer0 module of the PIC16C7X enhanced core products. It is an 8-bit overflow counter.
PIC14000 6.1 Timer0 Interrupt vice routine before re-enabling this interrupt. The Timer0 module interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. The timing of the Timer0 interrupt is shown in Figure 6-4. The TMR0 interrupt is generated when the Timer0 overflows from FFh to 00h. This overflow sets the T0IF bit. The interrupt can be masked by clearing bit T0IE (INTCON<5>).
PIC14000 6.2 Using Timer0 with External Clock 6.2.2 Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing. When the external clock input (pin RC3/T0CKI) is used for Timer0, it must meet certain requirements.
PIC14000 6.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program execution. To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to WDT. EXAMPLE 6-1: 1.
PIC14000 7.0 INTER-INTEGRATED CIRCUIT SERIAL PORT (I2C) The I2C module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The I2C module is compatible with the following interface specifications: • Inter-Integrated Circuit (I2C) • System Management Bus (SMBus) Note: 2 The I C module on PIC14000 only supports I2C mode.
PIC14000 I2CSTAT: I2C PORT STATUS REGISTER FIGURE 7-2: U U R R R R R R _ _ D/A P S R/W UA BF bit7 bit0 Register: I2CSTAT Address: 94h POR value: 00h W: Writable bit R: Readable bit U: Unimplemented, read as ‘0’ BF: Buffer full Receive 1 = Receive complete, I2CBUF is full 0 = Receive not complete, I2CBUF is empty Transmit 1 = Transmit in progress, I2CBUF is full 0 = Transmit complete, I2CBUF is empty UA: Update Address (10-bit I2C slave mode only) 1 = Indicate that the user needs to upda
PIC14000 FIGURE 7-3: R/W R/W I2CCON: I2C PORT CONTROL REGISTER R/W R/W R/W R/W R/W R/W WCOL I2COV I2CEN CKP I2CM3 I2CM2 I2CM1 I2CM0 bit7 bit0 Register: I2CCON Address: 14h POR value: 00h W: Writable bit R: Readable bit U: Unimplemented, read as ‘0’ I2CM<3:0>: I2C mode select I2C slave mode, 7-bit address I2C slave mode, 10-bit address I2C firmware controlled master mode (slave idle) I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address wi
PIC14000 I2C BUS TERMINOLOGY TABLE 7-1: Term Transmitter Receiver Master Slave Multi-master Description The device that sends the data to the bus. The device that receives the data from the bus. The device which initiates the transfer, generates the clock, and terminates the transfer. The device addressed by a master. More than one master device in a system. These masters can attempt to control the bus at the same time without corrupting the message.
PIC14000 7.3 Transfer Acknowledge accomplished by setting SMHOG (MISC<7>) high. Clearing MISC<7> will resume the data transfer. Figure 7-7 shows a data transfer waveform. All data must be transmitted per byte, with no limit to the number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (ACK). This is shown in Figure 7-6. When a slave-receiver doesn’t acknowledge the slave address or received data, the master must abort the transfer.
PIC14000 bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 7-10. When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START (Sr) must be generated.
PIC14000 7.4 Multi-Master Operation The I2C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur. 7.4.1 ARBITRATION FIGURE 7-11: MULTI-MASTER ARBITRATION (2 MASTERS) transmitter 1 loses arbitration DATA 1≠ SDA DATA 1 DATA 2 Arbitration takes place on the SDA line, while the SCL line is high.
PIC14000 FIGURE 7-13: I2C BLOCK DIAGRAM Internal data bus MISC<4> Read Write RC6/SCLA I2CBUF SCK RC7/SDAA 4:2 MUX Shift clock SDA I2CSR RD0/SCLB MSB RD1/SDAB Match Detect Addr_Match I2CADD Start and Stop bit detect 7.5 I2C Operation The I2C module in I2C mode fully implements all slave functions, and provides support in hardware to facilitate software implementations of the master functions.
PIC14000 7.5.1 SLAVE MODE In slave mode, the SCLx and SDAx pins must be configured as inputs (TRISC<7:6> or TRISD<1:0> are set). The I2C module will override the input state with the output data when required (slave-transmitter). When an address is matched or the data transfer from an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and then load the I2CBUF with the received value in the I2CSR.
PIC14000 7.5.1.1 ADDRESSING 4. Once the I2C module has been enabled, the I2C waits for a START to occur. Following the START, the 8-bits are shifted into the I2CSR. All incoming bits are sampled with the rising edge of the clock (SCL) line. The I2CSR<7:1> is compared to the I2CADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and I2COV bits are clear, the following things happen: • • • • 5. 6. 7. 8. 9. 7.5.1.
PIC14000 7.5.1.3 A I2CIF interrupt is generated for each data transfer byte. The I2CIF bit must be cleared in software, and the I2CSTAT register is used to determine the status of the byte. The I2CIF bit is set on the falling edge of the ninth clock pulse. TRANSMISSION When the R/W bit of the address byte is set and an address match occurs, the R/W bit of the I2CSTAT register is set. The received address is loaded into the I2CBUF The ACK pulse will be sent on the ninth bit, and the SCL pin is held low.
PIC14000 7.5.2 7.5.3 MASTER MODE Master mode operation is supported by interrupt generation on the detection of the START and STOP. The STOP(P) and START(S) bits are cleared from a reset or when the I2C module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are cleared. In master mode, the SCL and SDA lines are manipulated by changing the corresponding TRISC<7:6> or TRISD<1:0> bits to an output (cleared).
PIC14000 FIGURE 7-16: MISC REGISTER 9Eh Bit 7 MISC SMHOG Read/Write POR value 00h Bit Bit 6 Bit 5 SPGNDB SPGNDA Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CSEL SMBUS INCLKEN OSC2 OSC1 R/W R/W R/W R/W R/W R/W R/W R 0 0 0 0 0 0 0 X Name B7 SMHOG B6 SPGNDB B5 SPGNDA B4 I2CSEL B3 SMBus B2 INCLKEN B1 OSC2 B0 OSC1 Function SMHOG enable 1 = Stretch I2C CLK signal (hold low) when receive data buffer is full (refer to Section 7.5.4).
PIC14000 FIGURE 7-17: OPERATION OF THE I2C IN IDLE_MODE, RCV_MODE OR XMIT_MODE IDLE_MODE (7-bit): if (Addr_match) { Set interrupt; if (R/W = 1) { Send ACK = 0; set XMIT_MODE; } else if (R/W = 0) set RCV_MODE; } RCV_MODE: if ((I2CBUF=Full) OR (I2COV = 1)) { Set I2COV; Do not acknowledge; } else { transfer I2CSR → I2CBUF; send ACK = 0; } Receive 8-bits in I2CSR; Set interrupt; XMIT_MODE: While ((I2CBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if (ACK Received = 1) { End of transmissi
PIC14000 7.5.4 • A mechanism to stretch the I2C clock time has been implemented to support SMBus slave transactions. The SMHOG bit (MISC<7>) allows hardware to automatically force and hold the I2C clock line low when a data byte has been received. This prevents the SMBus master from overflowing the receive buffer in instances where the microcontroller may be to busy servicing higher priority tasks to respond to a I2C module interrupt.
PIC14000 NOTES: DS40122B-page 56 Preliminary 1996 Microchip Technology Inc.
PIC14000 8.0 ANALOG MODULES FOR A/D CONVERSION 8.1 Overview The PIC14000 includes analog components to create a slope A/D converter including: The maximum A/D timer count is 65,536. It can be clocked by the on-chip or external oscillator. At a 4 MHz oscillation frequency, the maximum conversion time is 16.38 ms for a full count. A typical conversion should complete before full-count is reached.
PIC14000 Caution: Reading or writing the ADTMR register during an A/D conversion cycle can produce unpredictable results and is not recommended. Note: A CPU interrupt will be generated if bit ADCIE (PIE1<1>) is set to ‘1’ (interrupt enabled). In addition, the Global Interrupt Enable and Peripheral Interrupt Enables (INTCON<7,6>) must also be set. Software is responsible for clearing the ADCIF flag prior to the next conversion cycle. Note that this interrupt can only occur once per conversion cycle.
PIC14000 FIGURE 8-2: EXAMPLE A/D CONVERSION CYCLE CAPTURE CLK ADTMR INCREMENTS ADRST ADCON0<1> ADTMR COUNT XX+1 XX+2 XX+3 XX XX+8 XX+9 COMPARE CDAC ADCIF, PIR1<1> (must be cleared by software) Capture Register FIGURE 8-3: 0Eh ADTMRL Read/Write POR value 00h FIGURE 8-4: XX+8 XX A/D CAPTURE TIMER (LOW BYTE) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 b7 b6 b5 b4 b3 b2 b1 b0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 A/D CAPTURE TIMER (HIGH BYTE) 0Fh Bi
PIC14000 8.4 A/D Comparator 8.5 The PIC14000 includes a high gain comparator for A/D conversions. The positive input terminal of the A/D comparator is connected to the output of an analog mux through an RC low-pass filter. The nominal time-constant for the RC filter is 3.5 µs. The negative input terminal is connected to the external 0.1 µF (nominal) ramp capacitor. TABLE 8-1: Analog Mux A total of 16 channels are internally multiplexed to the single A/D comparator positive input.
PIC14000 8.6 Programmable Current Source Four configuration bits (ADCON1<7:4>) are used to control a programmable current source for generating the ramp voltage to the A/D comparator. It allows compensation for full-scale input voltage, clock frequency and CDAC capacitor tolerance variations. The current values range from 0 to 33.75 µA (nominal) in 2.25 µA increments.
PIC14000 A/D Control Registers 8.7 Two A/D control registers are provided on the PIC14000 to control the conversion process. These are ADCON0 (1Fh) and ADCON1 (9Fh). Both registers are readable and writable.
PIC14000 TABLE 8-4: A/D CONTROL AND STATUS REGISTER 1 9Fh Bit 7 ADCON1 ADDAC3 Read/Write POR value 00h Bit 6 Bit 5 Bit 4 ADDAC2 ADDAC1 ADDAC0 Bit 3 Bit 2 Bit 1 Bit 0 PCFG3 PCFG2 PCFG1 PCFG0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit Name B7-B4 ADDAC3 ADDAC2 ADDAC1 ADDAC0 A/D Current Source Selects. Refer to Table 8-2.
PIC14000 8.8 A/D Speed, Resolution and Capacitor Selection The conversion time for the A/D converter on the PIC14000 can be calculated using the equation: Conversion Time = (1/Fosc) x 2N Where Fosc is the oscillator frequency and N is the number of bits of resolution desired. Therefore at 4MHz, the conversion time for 16 bits is 16.384 msec. Conversely, it is 256 µsec for 10 bits.
PIC14000 9.0 OTHER ANALOG MODULES 9.2.1 The PIC14000 has additional analog modules for mixed signal applications. These include: • • • • bandgap voltage reference comparators with programmable references internal temperature sensor voltage regulator control 9.1 Bandgap Voltage Reference The bandgap reference circuit is used to generate a 1.2V nominal stable voltage reference for the A/D and the low-voltage detector. The bandgap reference is channel 4 of the analog mux.
PIC14000 FIGURE 9-1: LEVEL-SHIFT NETWORKS VDD 5 µA (nominal) LSOFF (SLPCON<4>) Input Protection Diodes RA1/AN1 only SUM VDD External Capacitor (Optional) RA1/AN1 * RD5/AN5 To A/D mux, programmable reference comparators 100 kΩ (nominal) * ADZERO (ADCON<0>) LSOFF (SLPCON<4>) *These switches are a matched pair 9.3 Slope Reference Voltage Divider 9.
PIC14000 FIGURE 9-2: SLOPE REFERENCE DIVIDER ADOFF (SLPCON<0>) VREF Bandgap Reference + SREFHI _ To A/D MUX REFOFF (SLPCON<5>) SREFLO ~ KREF = SREFLO SREFHI 9 SREFLO SREFHI - SREFLO 9.5 Comparator and Programmable Reference Modules 9.5.1 COMPARATORS The PIC14000 includes two independent low-power comparators for comparing the programmable reference outputs to either the RA1/AN1 or RA5/AN5 pins.
PIC14000 Two registers PREFA (9Bh) and PREFB (9Ch) are used to select the reference output voltages. The PREFx<7:3> bits select the output from the coarse ladder, while PREFx<2:0> bits are for the fine-tune adjustment. Table 9-1 and Table 9-2 show the reference decoding. The reference outputs are also connected to two independent comparators, COMPA and COMPB. Thus, the references can be used to set the comparator trippoints. The A/D converter can also monitor the reference outputs via A/D channels 8 and 9.
PIC14000 TABLE 9-1: PROGRAMMABLE REFERENCE COARSE RANGE SELECTION Nominal Output Voltage Range (V) PREFx<7:3> Upper Middle Lower 0 1 1 1 1 0.8000 - 0.8500 0 1 1 1 0 0.7500 - 0.8000 0 1 1 0 1 0.7000 - 0.7500 0 1 1 0 0 0.6500 - 0.7000 0 1 0 1 1 0.6000 - 0.6500 0 1 0 1 0 0.5500 - 0.6000 0 1 0 0 1 0.5450 - 0.5500 0 1 0 0 0 0.5400 - 0.5450 0 0 1 1 1 0.5350 - 0.5400 0 0 1 1 0 0.5300 - 0.5350 0 0 1 0 1 0.5250 - 0.5300 0 0 1 0 0 0.
PIC14000 TABLE 9-2: PROGRAMMABLE REFERENCE FINE RANGE SELECTION Fractional Value Of The Coarse Range PREFx<2:0> 0 0 0 1/8 0 0 1 1/4 0 1 0 3/8 0 1 1 1/2 1 0 0 5/8 1 0 1 3/4 1 1 0 7/8 1 1 1 1 FIGURE 9-4: PROGRAMMABLE REFERENCE TRANSFER FUNCTION Upper Range 0.9 Middle Range Lower Range 0.8 0.7 VOLTS 0.6 0.5 0.4 0.3 0.2 0.1 7F 50 4F 00 C8 D7 F8 PREFx Value (hex) DS40122B-page 70 Preliminary 1996 Microchip Technology Inc.
PIC14000 FIGURE 9-5: COMPARATOR CONTROL REGISTER 9Dh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CMCON U CMBOUT CMBOE CPOLB U CMAOUT CMAOE CPOLA Read/Write — R R/W R/W — R R/W R/W POR value 00h 0 0 0 0 0 0 0 0 Bit Name B7 — B6 CMBOUT Function Unimplemented. Read as ‘0’. Comparator B Output Reading this bit returns the status of the comparator B output. Writes to this bit have no effect.
PIC14000 FIGURE 9-6: PREFA REGISTER 9Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PREFA PRA7 PRA6 PRA5 PRA4 PRA3 PRA2 PRA1 PRA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Read/Write POR value 00h Bit Name B7-B0 PRA7 PRA6 PRA5 PRA4 PRA3 PRA2 PRA1 PRA0 FIGURE 9-7: Function Programmable Reference A Voltage Select Bits. See Table 9-1 and Table 9-2 for decoding.
PIC14000 9.6 Voltage Regulator Output For systems with a main supply voltage above 6V, an inexpensive, low quiescent current voltage regulator can be formed by connecting the VREG pin to an external resistor and FET as shown in Figure 9-8. This circuit will provide a VDD of about 5V, after the voltage drop across the FET.
PIC14000 NOTES: DS40122B-page 74 Preliminary 1996 Microchip Technology Inc.
PIC14000 10.0 SPECIAL FEATURES OF THE CPU • • • • • What sets apart a microcontroller from other processors are special circuits to deal with the needs of real time applications. The PIC14000 has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC14000 10.2 Oscillator Configurations By selecting IN mode OSC1/PBTN becomes a digital input (with weak internal pull-up resistor) and can be read via bit MISC<0>. Writes to this location have no effect. The OSC1/PBTN input is capable of generating an interrupt to the CPU if enabled (Section 10.6). Also, the OSC2 pin becomes a digital output for general purpose use and is accessed via MISC<1>. Writes to this bit directly affect the OSC2 pin. Reading this bit returns the contents of the output latch.
PIC14000 10.2.2 TABLE 10-2: CRYSTAL OSCILLATOR/CERAMIC RESONATOR In HS mode, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. A parallel cut crystal is required. Use of a series cut crystal may give a frequency outside of the crystal manufacturer’s specifications. When in HS mode, the device can have an external clock source to drive the OSC1 pin.
PIC14000 Figure 10-6 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region. FIGURE 10-6: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330kΩ 330kΩ 74AS04 74AS04 To Other Devices PIC14000 74AS04 OSC1 0.1µF XTAL 10.
PIC14000 TABLE 10-3: STATUS BITS AND THEIR SIGNIFICANCE POR TO PD 0 1 1 Power-On Reset 0 0 X Illegal, TO is set on POR 0 X 0 Illegal, PD is set on POR 1 0 1 WDT reset during normal operation 1 0 0 WDT time-out wakeup from sleep 1 1 1 MCLR reset during normal operation 1 1 0 MCLR reset during SLEEP or HIBERNATE, or interrupt wake-up from SLEEP or HIBERNATE. 10.4 Meaning Low-Voltage Detector 10.5.2 The PIC14000 contains an integrated low-voltage detector.
PIC14000 10.5.5 TIMEOUT SEQUENCE On power-up the time-out sequence is as follows: First the PWRT time-out is invoked after POR has expired. The OST is activated only in HS (crystal oscillator) mode. The total time-out will vary based on the oscillator configuration and PWRTE status. For example, in IN mode, with PWRTE unprogrammed (PWRT disabled), there will be no time-out delay at all. Figure 13-4 depicts the power-on reset time-out sequences.
PIC14000 TABLE 10-5: Register W INDF TMR0 PCL RESET CONDITIONS FOR REGISTERS Address Power-on Reset MCLR reset during - normal operation - SLEEP WDT time-out during normal operation - xxxx xxxx uuuu uuuu uuuu uuuu 00h/80h - - - 01h xxxx xxxx uuuu uuuu uuuu uuuu 02h/82h 0000h 0000h PC + 1(2) ?uuu(3) Wake-up from SLEEP through interrupt Wake up from SLEEP through WDT time-out uuu? ?uuu(3) STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu 05h ---- xxxx ---- u
PIC14000 10.6 Interrupts The return from interrupt instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit to re-enable interrupts.
PIC14000 10.6.1 ware in the interrupt service routine before re-enabling the interrupt. This interrupt can wake up the processor from SLEEP if PBIE bit is set (interrupt enabled) prior to going into SLEEP mode. The status of the GIE bit determines whether or not the processor branches to the interrupt vector following wake-up. The timing of the external interrupt is shown in Figure 10-10.
PIC14000 10.6.2 10.6.4 TIMER0 INTERRUPT An overflow (FFh → 00h) in Timer0 will set the T0IF (INTCON<2>) flag. Setting T0IE (INTCON<5>) enables the interrupt. 10.6.3 PORTC INTERRUPT ON CHANGE An input change on PORTC<7:4> sets RCIF (PIR1<2>). Setting RCIE (PIE1<2>) enables the interrupt. For operation of PORTC, refer to Section 5.2. Note: CONTEXT SWITCHING DURING INTERRUPTS During an interrupt, only the return PC value is saved on the stack.
PIC14000 10.7 Watchdog Timer (WDT) The WDT can be permanently disabled by programming the configuration bit WDTE as a ‘0’. Its oscillator can be shut down to conserve battery power by entering HIBERNATE Mode. Refer to Section 10.8.3 for more information on HIBERNATE mode. The watchdog timer is realized as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the IN oscillator used to generate the CPU and A/D clocks.
PIC14000 10.7.1 10.7.2 WDT PERIOD The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION registers. Thus, time-out periods up to 2.3 seconds can be realized.
PIC14000 10.8.1 SLEEP MODE The SLEEP mode is entered by executing a SLEEP instruction. If SLEEP mode is enabled, the WDT will be cleared but keep running. The PD bit in the STATUS register is cleared, the TO bit is set, and on-chip oscillators are shut off, except the WDT RC oscillator, which continues to run. The I/O ports maintain the status they had before the SLEEP command was executed (driving high, low, or high-impedance). It is an option while in SLEEP mode to leave the on-chip oscillator running.
PIC14000 FIGURE 10-12: SLPCON REGISTER 8Fh SLPCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 HIBEN — REFOFF LSOFF OSCOFF CMOFF R/W U R/W R/W R/W R/W R/W R/W 0 0 1 1 1 1 1 1 Read/Write POR value 3Fh Bit Name B7 HIBEN B6 – B5 REFOFF B4 LSOFF B3 OSCOFF B2 CMOFF B1 TEMPOFF B0 ADOFF DS40122B-page 88 Bit 1 Bit 0 TEMPOFF ADOFF Function Hibernate Mode Select 1 = Hibernate mode enable 0 = Normal operating mode Unimplemented.
PIC14000 FIGURE 10-13: WAKE-UP FROM SLEEP AND HIBERNATE THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INTERRUPT Flag (5) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Inst(PC) = SLEEP Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: 5: 10.
PIC14000 NOTES: DS40122B-page 90 Preliminary 1996 Microchip Technology Inc.
PIC14000 11.0 INSTRUCTION SET SUMMARY The PIC14000’s instruction set is the same as PIC16CXX. Each instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode field descriptions.
PIC14000 TABLE 11-2: Mnemonic, Operands PIC14000 INSTRUCTION SET Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f
PIC14000 11.1 Instruction Descriptions ANDLW And Literal with W Syntax: [ label ] ANDLW 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 (W) + k → (W) Operation: (W) .AND. (k) → (W) C, DC, Z Status Affected: Z ADDLW Add Literal and W Syntax: [ label ] ADDLW Operands: Operation: Status Affected: Encoding: 11 k 111x kkkk kkkk Encoding: 11 Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register.
PIC14000 BCF Bit Clear f BTFSC Bit Test, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 f,b 00bb bfff ffff Description: Bit 'b' in register 'f' is cleared.
PIC14000 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 127 Operation: 00h → (f) 1→Z Status Affected: Z Operation: skip if (f) = 1 Status Affected: None Encoding: Description: 01 11bb bfff ffff If bit 'b' in register 'f' is '1' then the next instruction is skipped.
PIC14000 CLRWDT Clear Watchdog Timer DECF Decrement f Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d Operands: None Operands: Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (dest) Status Affected: Z Status Affected: Encoding: Description: Encoding: TO, PD 00 0000 0110 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC14000 GOTO Unconditional Branch INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 2047 Operands: Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 None Status Affected: None Status Affected: Encoding: GOTO k 10 1kkk kkkk kkkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>.
PIC14000 IORWF Inclusive OR W with f MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .OR. (f) → (dest) Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 IORWF f,d 0100 dfff ffff Description: Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the W register. If 'd' is 1 the result is placed back in register 'f'.
PIC14000 NOP No Operation RETFIE Return from Interrupt Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: No operation Operation: Status Affected: None TOS → PC, 1 → GIE Status Affected: None Encoding: 00 NOP 0000 0xx0 0000 No operation. Encoding: Words: 1 Description: Cycles: 1 Description: Example RETFIE 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC.
PIC14000 RETURN Return from Subroutine RRF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: None Operation: See description below Status Affected: C Encoding: Description: 00 0000 0000 1000 Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.
PIC14000 SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k - (W) → (W) 0 ≤ f ≤ 127 d ∈ [0,1] Status Affected: C, DC, Z Encoding: 11 Description: SUBLW k 110x kkkk kkkk The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.
PIC14000 SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W Syntax: [ label ] SWAPF f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Operation: (W) .XOR. k → (W) Status Affected: Z Status Affected: None Encoding: Encoding: Description: 00 1110 dfff ffff The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register.
PIC14000 12.0 DEVELOPMENT SUPPORT 12.1 Development Tools 12.
PIC14000 12.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC14000 MPASM allows full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. MPASM has the following features to assist in developing software for specific use applications. 12.14 • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability.
1996 Microchip Technology Inc.
PIC14000 13.0 ELECTRICAL CHARACTERISTICS FOR PIC14000 ABSOLUTE MAXIMUM RATINGS † Ambient temperature under bias.............................................................................................................-55°C to+ 125°C Storage Temperature ............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................
PIC14000 13.1 DC Characteristics: PIC14000 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ + 85°C for industrial and 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD = 2.7V to 6.0V DC CHARACTERISTICS Characteristic Supply Voltage Sym VDD Min Typ† Max Units Conditions 2.7 — 6.0 V IN or HS at Fosc ≤ 4 MHz 4.5 — 5.5 V HS at Fosc > 4 MHz RAM Data Retention Voltage (Note 1) VDR — 1.
PIC14000 13.2 DC Characteristics: PIC14000 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ + 85°C for industrial and 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in Section 13.1. Sym Min Typ† Max Units Conditions DC CHARACTERISTICS Characteristic Input Low Voltage I/O ports VIL Schmitt Trigger mode VSS — 0.2VDD V SMBus mode (RC7, RC6, RD0, RD1) VSS — 0.6 V MCLR, OSC1 (in IN mode) Vss — 0.
PIC14000 13.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC14000 13.4 Timing Diagrams and Specifications FIGURE 13-1: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 3 1 3 4 4 2 CLKOUT TABLE 13-1: Parameter No.
PIC14000 FIGURE 13-2: LOAD CONDITIONS Load condition 2 Load condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 Ω CL = 50 pF 15 pF DS40122B-page 112 for all pins except OSC2 for OSC2 output Preliminary 1996 Microchip Technology Inc.
PIC14000 FIGURE 13-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 12 19 18 14 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 13-2 for load conditions TABLE 13-2: Parameter No.
PIC14000 FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER (HS MODE) AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 34 I/O Pin Note: Refer to Figure 13-2 for load conditions TABLE 13-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC14000 FIGURE 13-5: TIMER0 CLOCK TIMINGS T0CKI 41 40 42 Note: Refer to Figure 13-2 for load conditions. TABLE 13-4: TIMER0 CLOCK REQUIREMENTS Parameter No. Sym Characteristic 40 Tt0H T0CKI High Pulse Width No Prescaler Min Typ† Max Units 0.5 TCY + 20* — — ns 10* — — ns 0.5 TCY + 20* — — ns 10* — — ns TCY + 40* N — — ns With Prescaler 41 Tt0L T0CKI Low Pulse Width No Prescaler With Prescaler 42 * † Tt0P T0CKI Period Conditions N = prescale value (1, 2, 4, ...
PIC14000 FIGURE 13-6: I2C BUS START/STOP BITS TIMING SCL 91 81 93 83 92 82 90 80 SDA START Condition STOP Condition Note: Refer to Figure 13-2 for load conditions TABLE 13-5: I2C BUS START/STOP BITS REQUIREMENTS Parameter No.
PIC14000 FIGURE 13-7: I2C BUS DATA TIMING 103 93 102 92 100 90 91 101 SCL 90 80 106 96 107 97 81 91 82 92 SDA IN 100 110 99 109 99 109 SDA OUT Note: Refer to Figure 13-2 for load conditions TABLE 13-8: I2C BUS DATA REQUIREMENTS Parameter No. Sym Characteristic 100 THIGH Clock high time Min Max Units 100 kHz mode 4.0 — µs PIC14000 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs PIC14000 must operate at a minimum of 10 MHz I2C Module 101 TLOW Clock low time 1.
PIC14000 13.5 DC and AC Characteristics Graphs and Tables for PIC14000 FIGURE 13-10: TYPICAL IPD3 vs VDD AT 25°C FIGURE 13-9: TYPICAL IPD4 VS VDD AT 25°C TO BE DETERMINED. TO BE DETERMINED. FIGURE 13-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN HS MODE) vs VDD 3.60 3.40 3.20 ) 5°C to 8 C 40° x () Ma YP 5°C CT to 8 C 25° ° (-40 Min 3.00 2.80 VTH (Volts) 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.
PIC14000 FIGURE 13-12: TYPICAL OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, 25°C) 10,000 6.0 5.5 5.0 4.5 4.0 3.5 3.0 IDD (µA) 1,000 100 10 1 10,000 100,000 1,000,000 10,000,000 100,000,000 Frequency (Hz) FIGURE 13-13: MAXIMUM OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, -40° TO +85°C) TO BE DETERMINED. 1996 Microchip Technology Inc.
PIC14000 FIGURE 13-14: MAXIMUM IPD1 VS FREQ (EXT CLOCK, -40° TO +85°C) TO BE DETERMINED. FIGURE 13-15: WATCHDOG TIMER TIME-OUT PERIOD (TWDT) VS. TEMPERATURE (TYPICAL) VDD=5V WDT Time-Out Period (no Prescaler, mSec) 24 22 20 18 16 14 12 10 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) DS40122B-page 120 Preliminary 1996 Microchip Technology Inc.
PIC14000 FIGURE 13-16: WDT TIMER TIME-OUT PERIOD VS VDD FIGURE 13-18: IOH VS VOH, VDD = 3V* 0 50.0 45.0 -5 40.0 C Min @ +85˚ -10 30.0 IOH (mA) WDT period (ms) 35.0 Ma x, 8 5˚C 25.0 Max, 20.0 Typ, 25˚C Typ @ -15 70˚C 25˚C -20 -40˚C Max @ 15.0 Min, 0˚C 10.0 -25 Min, -40˚C 0 0.5 1 5.0 2 3 4 5 6 1.5 2 2.
PIC14000 FIGURE 13-20: IOL VS VOL, VDD = 3V* FIGURE 13-21: IOL VS VOL, VDD = 5V* 35 90 Min @ -40°C 30 80 Min @ -40°C 70 25 60 Typ @ 25°C Typ @ 25°C IOL (mA) IOL (mA) 20 15 Min @ +85°C 50 Min @ +85°C 40 30 10 20 5 10 0 0 0.5 1 1.5 2 2.5 0 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (Volts) VOL (Volts) *NOTE: All pins except OSC2 DS40122B-page 122 Preliminary 1996 Microchip Technology Inc.
PIC14000 14.0 ANALOG SPECIFICATIONS: PIC14000-04 (COMMERCIAL, INDUSTRIAL) Standard Operating Conditions (unless otherwise stated) -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated. Operating Temperature: Characteristic Sym. Min. Typ. Max. Units Conditions Notes vo(vref) 1.14 1.19 1.24 V Turn-on Settling Time to < 0.
PIC14000 Standard Operating Conditions (unless otherwise stated) -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated. Operating Temperature: Characteristic Sym. Min. Typ. Max. Units Conditions Notes Output Linearity lin(temp) — TBD — Operating Current (sensor on) idd(temp) — 150 250 µA TEMPOFF = 0 2 Operating Current (sensor off) idd(temp) — 0 — µA TEMPOFF = 1 2 1.14 1.19 1.
PIC14000 Standard Operating Conditions (unless otherwise stated) -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated. Operating Temperature: Characteristic Sym. Min. Typ. Max. Units Conditions Notes 0.304 0.384 0.464 V 0.114 0.144 0.174 V resc(pref) resf(pref) 38.0 4.0 48.0 5.0 58.0 6.
PIC14000 Standard Operating Conditions (unless otherwise stated) -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated. Operating Temperature: Characteristic Sym. Min. Typ. Max. Units Conditions Notes Programmable Reference Comparator(s) Input Offset Voltage ioff(comp) -10 3 10 mV Input Common Mode Voltage Range cmr(comp) 0 — VDD-1.4 V Differential Voltage Gain Tested at 0.
PIC14000 Standard Operating Conditions (unless otherwise stated) -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated. Operating Temperature: Characteristic Sym. Min. Typ. Max. Units Calibration Accuracy Conditions Notes All parameters calibrated at VDD = 3, 5 5V, TA = 25°C unless noted. Accuracy Typ Max Slope Reference Ratio Parameter Sym. KREF Resolution Units 0.015% — .
PIC14000 FIGURE 14-1: BANDGAP REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 1.194 1.192 Reference Output (Volts) 1.190 1.188 1.186 1.184 1.182 1.180 1.178 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) FIGURE 14-2: PROGRAMMABLE CURRENT SOURCE vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 2.7 Current Source Output (uA) 2.5 2.3 2.1 1.9 1.7 -40 -30 -20 -10 1996 Microchip Technology Inc.
PIC14000 FIGURE 14-3: TEMPERATURE SENSOR OUTPUT VOLTAGE vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 1.4 Temperature Sensor Output (Volts) 1.3 1.2 1.1 1.0 0.9 0.8 -40 -30 -20 -10 0 10 20 40 50 30 60 70 80 90 100 Temperature (°C) FIGURE 14-4: SLOPE REFERENCE RATIO (KREF) vs. SUPPLY VOLTAGE (TYPICAL DEVICES SHOWN) 0.1260 Slope Reference Ratio (KREF) 0.1258 0.1256 0.1254 0.1252 0.1250 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.
PIC14000 FIGURE 14-5: SLOPE REFERENCE RATIO (KREF) vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 0.1260 Slope Reference Ratio (KREF) 0.1258 0.1256 0.1254 0.1252 0.1250 0.1248 0.1246 -40 -20 0 20 40 60 Temperature (°C) Fixed Bandgap Reference Voltage 80 100 FIGURE 14-6: PROGRAMMABLE REFERENCE OUTPUT vs. TEMPERATURE (TYPICAL) Programmable Reference Output (Volts) 0.7 0.6 0.5 0.4 0.3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) 1996 Microchip Technology Inc.
PIC14000 FIGURE 14-7: INTERNAL RC OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE (TYPICAL DEVICES SHOWN) 4.3 4.2 Oscillator Frequency (MHz) 4.1 4.0 3.9 3.8 3.7 3.6 3.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Supply Voltage (Volts) FIGURE 14-8: INTERNAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 4.4 4.3 Oscillator Frequency (MHz) 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.
PIC14000 NOTES: 1996 Microchip Technology Inc.
1996 Microchip Technology Inc. PIC14000 20 of O em M o ry ) ) es ( 4 x1 r s) wo M W /P e ar Memory ) ds M o t r Po T) R SA ,U 2C I/I s) e( l du Peripherals g in m am Features 4K 192 yt (b TMR0 ADTMR am — I2C/ SMBus — SP 14 11 22 2.7-6.0 Yes — Internal Oscillator, Bandgap Reference, Temperature Sensor, Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE, Comparators with Programmable References (2) ag es 28-pin DIP, SOIC, SSOP (.
Preliminary 20 20 20 20 20 20 20 20 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A im um qu — 2K — 2K 1K 512 — 512 RO en 2K — 2K — — — 512 — — — 73 73 72 72 25 24 25 25 25 25 RA D M M at a Fr e 512 yte s) em or TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 ) 12 12 20 20 12 20 12 12 12 12 ns 2.5-6.25 2.0-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.
1996 Microchip Technology Inc. Preliminary 20 20 20 20 20 PIC16C556 PIC16C558 PIC16C620 PIC16C621 PIC16C622 2K 1K 512 2K 1K 512 128 80 80 128 80 80 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 H 2 2 2 — — — Yes Yes Yes — — — 3 4 4 4 3 3 13 13 13 13 13 13 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.
DS40122B-page 136 Preliminary 20 PIC16C65 Features — 4K 4K — 2K 2K — 4K — 2K 2K 4K — — 2K — — 4K — 2K — — 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 H 2 SPI/I2C, Yes USART 11 11 11 2 SPI/I2C, Yes USART 2 SPI/I2C, Yes USART 8 8 8 10 10 7 7 7 Yes 1 SPI/I2C Yes Yes 1 SPI/
1996 Microchip Technology Inc.
Preliminary 10 10 10 10 PIC16F84(1) PIC16CR84(1) PIC16F83(1) PIC16CR83(1) F — 512 — 1K — — — — — 1K — 1K — — 512 EE (M 36 36 68 68 Da 64 64 64 64 ta Da em 64 ta y or P ( er T TMR0 TMR0 TMR0 TMR0 o M 4 4 4 4 4 Peripherals ) ts ol (V Features 13 13 13 13 13 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.
1996 Microchip Technology Inc. Preliminary y or em M M T) R SA ) (s le u od ls ne n ha Features 4K 8 PIC16C924 176 TMR0, 1 SPI/I2C TMR1, TMR2 176 TMR0, 1 SPI/I2C TMR1, TMR2 am — — 5 — 4 Com 32 Seg 4 Com 32 Seg ,U 9 8 25 25 27 27 3.0-6.0 3.0-6.0 Yes Yes — — 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
Preliminary 25 25 25 25 25 PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 im um 8K — 4K — 2K eq ue 4K — 2K — — RO EP O pe r RO n 454 454 454 232 232 232 M of nc y M io at o Pr R y or em (M ) Hz M m ds (W or or y ) ) es yt (b m gr a D AM Fr 2K ) TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 Se Yes Yes Yes Yes Yes Yes lP or t( (U Yes Yes Ye
PIC14000 A.9 Pin Compatibility Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55.
PIC14000 NOTES: DS40122B-page 142 Preliminary 1996 Microchip Technology Inc.
PIC14000 INDEX A DC Characteristics ........................................................... 108 DECF Instruction................................................................ 96 DECFSZ Instruction ........................................................... 96 Development Support ...................................................... 103 Development Tools .......................................................... 103 Digit Carry bit .....................................................................
PIC14000 PCON................................................................................. 22 PD ...................................................................................... 79 PICDEM-1 Low-Cost PIC16/17 Demo Board........... 103, 104 PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 103, 104 PICDEM-3 Low-Cost PIC16C9XXX Demo Board............ 104 PICMASTER RT In-Circuit Emulator............................. 103 PICSTART Low-Cost Development System ................. 103 PIE1 ...................
PIC14000 Figure 7-15: Figure 7-16: Figure 7-17: Figure 7-18: Figure 8-1: Figure 8-2: Figure 8-3: Figure 8-4: Figure 8-5: Figure 8-6: Figure 9-1: Figure 9-2: Figure 9-3: Figure 9-4: Figure 9-5: Figure 9-6: Figure 9-7: Figure 9-8: Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 10-5: Figure 10-6: Figure 10-7: Figure 10-8: Figure 10-9: Figure 10-10: Figure 10-11: Figure 10-12: Figure 10-13: Figure 10-14: Figure 11-1: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figu
PIC14000 Table 13-2: Table 13-3: Table 13-4: Table 13-5: Table 13-8: Table A-1: CLKOUT and I/O Timing Requirements .. 113 Reset, Watchdog Timer, Oscillator Start-up Timer And Power-up Timer Requirements .......................................... 114 Timer0 Clock Requirements .................... 115 I2C Bus Start/stop Bits Requirements...... 116 I2C Bus Data Requirements .................... 117 Pin Compatible Devices ...........................
PIC14000 ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
PIC14000 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC14000 PIC14000 PRODUCT IDENTIFICATION SYSTEM To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales offices. PART NO. -XX X /XX XXX 1996 Microchip Technology Inc.
PIC14000 NOTES: DS30444C-page 150 Preliminary 1996 Microchip Technology Inc.
PIC14000 NOTES: 1996 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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