Information

 2010-2012 Microchip Technology Inc. DS80502E-page 5
PIC12(L)F1822/PIC16(L)F1823
TABLE 3: INSTRUCTION CYCLE DELAY
COUNTS FOR OTHER F
OSC
AND T
AD COMBINATIONS
Affected Silicon Revisions
3. Module: APFCON
3.1 Timer1 Gate
The APFCON register is normally used to remap
the T1 Gate to an alternate pin. The T1GSEL bit of
the APFCON register is found to be not writable
and therefore the T1Gate pin cannot be
remapped. The default value for the T1GSEL bit is
0 and, therefore, the T1Gate will be found on RA4.
This affects the PIC16(L)F1823 devices only.
Work around
None.
Affected Silicon Revisions
4. Module: Enhanced Capture Compare
PWM (ECCP)
4.1 Enhanced PWM
When the PWM is configured for Full-Bridge mode
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increase the duty cycle to a value greater than 0%
before changing directions.
Affected Silicon Revisions
4.2 Enhanced PWM
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increase the duty cycle to a value greater than 0%
before enabling/disabling steering to port pins.
Affected Silicon Revisions
5. Module: Clock Switching
5.1 OSTS Status Bit
When the 4xPLL is enabled, the Oscillator Start-up
Time-out Status (OSTS) bit always remains clear.
Work around
None.
Affected Silicon Revisions
6. Module: Timer1 Gate
6.1 Timer1 Gate Toggle mode
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full-cycle length of a
Timer1 Gate signal. To perform this function, the
Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of
the gate signal. Timer1 Gate Toggle mode is
enabled by setting the T1GTM bit of the T1GCON
register. When working properly, clearing either
the T1GTM bit or the TMR1ON bit would also clear
the output value of this flip-flop, and hold it clear.
This is done in order to control which edge is being
measured. The issue that exists is that clearing the
TMR1ON bit does not clear the output value of the
flip-flop and hold it clear.
Work around
Clear the T1GTM bit in the T1GCON register to
clear and hold clear the output value of the flip-
flop.
Affected Silicon Revisions
FOSC TAD
Instruction Cycle Delay
Counts
32 MHz
FOSC/64 172
F
OSC/32 86
16 MHz
FOSC/64 172
FOSC/32 86
F
OSC/16 43
8 MHz
FOSC/32 86
FOSC/16 43
A6 A8 A9
X
A6 A8 A9
X
A6 A8 A9
X
A6 A8 A9
X
A6 A8 A9
XXX
A6 A8 A9
X