Information

PIC12(L)F1822/PIC16(L)F1823
DS80502E-page 4  2010-2012 Microchip Technology Inc.
2. Module: ADC
2.1 Analog-to-Digital Converter (ADC)
Under certain device operating conditions, the
ADC conversion may not complete properly. When
this occurs, the ADC Interrupt Flag (ADIF) does
not get set, the GO/DONE
bit does not get cleared
and the conversion result does not get loaded into
the ADRESH and ADRESL result registers.
Work around
Method 1: Select the dedicated RC
oscillator as the ADC conversion
clock source, and perform all
conversions with the device in
Sleep.
Method 2: Provide a fixed delay in software
to stop the A-to-D conversion
manually, after all 10 bits are
converted, but before the
conversion would complete
automatically. The conversion is
stopped by clearing the GO/
DONE
bit in software. The GO/
DONE
bit must be cleared during
the last ½ T
AD cycle, before the
conversion would have
completed automatically. Refer to
Figure 1 for details.
FIGURE 1: INSTRUCTION CYCLE DELAY CALCULATION EXAMPLE
In Figure 1, 88 instruction cycles (TCY) will be
required to complete the full conversion. Each T
AD
cycle consists of 8 TCY periods. A fixed delay is
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
EXAMPLE 1: CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
For other combinations of FOSC, TAD values and
instruction cycle delay counts, refer to Tabl e 3 .
FOSC = 32 MHz
TCY = 4/32 MHz = 125 nsec
TAD = 1 µsec, ADCS = FOSC/32
88 TCY
84 TCY
8 TCY
4 TCY
1 TAD
11 TAD
Stop the A/D conversion
between 10.5 and 11 T
AD
cycles.
See the Analog-to-Digital
Conversion Timing diagram
in the Analog-to-Digital
Converter section of the
DS41413B data sheet.
}
See the ADC Clock Period (T
AD) vs. Device Operating Frequencies table, in the Analog-to-Digital Converter
section of the DS41413B data sheet.
Note: The exact delay time will depend on the
choice of F
OSC and the TAD divisor
(ADCS) selection. The T
CY counts shown
in the timing diagram above apply to this
example only. Refer to Table 3 for the
required delay counts for other
configurations.
BSF ADCON0, GO/DONE; Start ADC conversion
; Provide 86
instruction cycle
delay here
BCF ADCON0, GO/DONE
; Terminate the
conversion manually
MOVF ADRESH, W ; Read conversion
result