Information

 2010-2012 Microchip Technology Inc. DS80502E-page 3
PIC12(L)F1822/PIC16(L)F1823
Silicon Errata Issues
1. Module: Oscillator
1.1 HS Oscillator
The HS oscillator requires a minimum voltage of
3.0 volts (at 65°C or less) to operate at 20 MHz.
Work around
None.
Affected Silicon Revisions
1.2 OSCSTAT bits: HFIOFR and HFIOFS
When HFINTOSC is selected, the HFIOFR and
HFIOFS bits will become set when the oscillator
becomes ready and stable. Once these bits are
set, they become “stuck”, indicating that
HFINTOSC is always ready and stable. If the
HFINTOSC is disabled, the bits fail to be cleared.
Work around
None.
Affected Silicon Revisions
1.3 Clock Switching
When switching clock sources between INTOSC
clock source and an external clock source, one
corrupted instruction may be executed after the
switch occurs.
This issue does not affect Two-Speed Start-up or
the Fail-Safe Clock Monitor operation.
Work around
When switching from an external oscillator clock
source, first switch to 16 MHz HFINTOSC. Once
running at 16 MHz HFINTOSC, configure IRCF to
run at desired internal oscillator frequency.
When switching from an internal oscillator
(INTOSC) to an external oscillator clock source,
first switch to HFINTOSC High-Power mode (8
MHz or 16 MHz). Once running from HFINTOSC,
switch to the external oscillator clock source.
Affected Silicon Revisions
1.4 Oscillator Start-up Timer (OST) bit
During the Two-Speed Start-up sequence, the
OST is enabled to count 1024 clock cycles. After
the count is reached, the OSTS bit is set, the sys-
tem clock is held low until the next falling edge of
the external crystal (LP, XT or HS mode), before
switching to the external clock source.
When an external oscillator is configured as the
primary clock and Fail-Safe Clock mode is enabled
(FCMEN = 1), any of the following conditions will
result in the Oscillator Start-up Timer (OST) failing
to restart:
•MCLR
Reset
• Wake from Sleep
• Clock change from INTOSC to Primary Clock
This anomaly will manifest itself as a clock failure
condition for external oscillators which take longer
than the clock failure time-out period to start.
Work around
None.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A9).
A6 A8 A9
X
A6 A8 A9
XX
A6 A8 A9
XX
A6 A8 A9
XX