Datasheet

PIC12F752/HV752
DS41576B-page 90 Preliminary  2011 Microchip Technology Inc.
11.6 Blanking Control
Input blanking is a function whereby the event inputs
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the
turn-on/off of power components from generating a
false input event.
The COG contains two 4-bit blanking counters. The
counters are cross coupled with the events they are
blanking. The falling event blanking counter is used to
blank rising input events and the rising event blanking
counter is used to blank falling input events. Once
started, blanking extends for the time specified by the
corresponding blanking counter.
Blanking is timed by counting COG_clock periods from
zero up to the value in the blanking count register. Use
Equation 11-1 to calculate blanking times.
11.6.1 RISING EVENT INPUT BLANKING
The falling event blanking counter inhibits the rising
input from triggering a rising event. The falling event
blanking time starts when the falling event output drive
goes true.
The falling event blanking time is set by the value con-
tained in the GxBLKF<3:0> bits of the COGxBLK reg-
ister. Blanking times are calculated using the formula
shown in Equation 11-1.
When the GxBLKF<3:0> value is zero, falling event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
11.6.2 FALLING EVENT INPUT BLANKING
The rising event blanking counter inhibits the falling
input from triggering a falling event. The rising event
blanking time starts when the rising event output drive
goes true.
The rising event blanking time is set by the value
contained in the GxBLKR<3:0> bits of the COGxBLK
register.
When the GxBLKR<3:0> value is zero, rising event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.
11.6.3 BLANKING TIME UNCERTAINTY
When the rising and falling events that trigger the
blanking counters are asynchronous to the
COG_clock, it creates uncertainty in the blanking time.
The maximum uncertainty is equal to one COG_clock
period. Refer to Equation 11-1 and Example 11-1 for
more detail.
11.7 Phase Delay
It is possible to delay the assertion of the rising event.
This is accomplished by placing a non-zero value in
COGxPH register. Refer to Register 11-6 and
Figure 11-3 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal
switching to the actual assertion of the events is calcu-
lated the same as the dead-band and blanking delays.
Please see Equation 11-1.
When the COGxPH value is zero, phase delay is dis-
abled and the phase delay counter output is true,
thereby, allowing the event signal to pass straight
through to complementary output driver flop.
11.7.1 CUMULATIVE UNCERTAINTY
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the
phase delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or
phase delay stages, and the blanking stage comes
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage.
EQUATION 11-1: PHASE, DEAD-BAND,
AND BLANKING TIME
CALCULATION
T
min
Count=
T
max
Count 1+
F
COG_clock
--------------------------=
T
uncertainty
T
max
T
min
–=
T
uncertainty
1
F
COG_clock
--------------------------=
Also:
Where:
T Count
Phase Delay GxPH<3:0>
Rising Dead Band GxDBR<3:0>
Falling Dead Band GxDBF<3:0>
Rising Event Blanking GxBLKR<3:0>
Falling Event Blanking GxBLKF<3:0>
COG_clock
F