Datasheet

PIC12F752/HV752
DS41576B-page 74 Preliminary  2011 Microchip Technology Inc.
9.1 HLT Operation
The clock input to the HLT module is the system
instruction clock (F
OSC/4). HLTMR1 increments on
each rising clock edge.
A 4-bit counter/prescaler on the clock input provides the
following prescale options:
• Direct input
•Divide-by-4
•Divide-by-16
The prescale options are selected by the prescaler
control bits, H1CKPS<1:0> of the HLT1CON0 register.
The value of HLTMR1 is compared to that of the Period
register, HLTPR1, on each clock cycle. When the two
values match,then the comparator generates a match
signal as the HLTimer1 output. This signal also resets
the value of HLTMR1 to 00h on the next clock rising
edge and drives the output counter/postscaler (see
Section 9.2 “HLT Interrupt”).
The HLTMR1 and HLTPR1 registers are both directly
readable and writable. The HLTMR1 register is cleared
on any device Reset, whereas the HLTPR1 register
initializes to FFh. Both the prescaler and postscaler
counters are cleared on any of the following events:
• A write to the HLTMR1 register
• A write to the HLT1CON0 register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•MCLR
Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
9.2 HLT Interrupt
The HLT can also generate an optional device interrupt.
The HLTMR1 output signal (HLTMR1-to-HLTPR1
match) provides the input for the 4-bit counter/
postscaler. The overflow output of the postscaler sets
the HLTMR1IF bit of the PIR1 register. The interrupt is
enabled by setting the HLTMR1 Match Interrupt Enable
bit, HLTMR1IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, H1OUTPS<3:0>, of the HLT1CON0 register.
9.3 Peripheral Resets
Resets driven from the selected peripheral output pre-
vents the HLTMR1 from matching the HLTPR1 register
and generating an output. In this manner, the HLT can
be used as a hardware time limit to other peripherals.
In this device, the primary purpose of the HLT is to limit
the COG PWM duty cycle. Normally, the COG opera-
tion uses analog feedback to determine the PWM duty
cycle. The same feedback signal is used as an HLT
Reset input. The HLTPR1 register is set to occur at the
maximum allowed duty cycle. If the analog feedback to
the COG exceeds the maximum time, then an
HLTMR1-to-HLTPR1 match will occur and generate the
output needed to limit the COG drive output.
The HLTMR1 can be reset by one of several selectable
peripheral sources. Reset inputs include:
• CCP1 output
• Comparator 1 output
• Comparator 2 output
The Reset input is selected with the H1ERS<2:0> bits
of the HLT1CON1 register.
HLTMR1 Resets are synchronous with the HLT clock.
In other words, HLTMR1 is cleared on the rising edge
of the HLT clock after the enabled Reset event occurs.
The Reset can be enabled to occur on the rising and
falling input event. Rising and falling event enables are
selected with the respective H1REREN and H1FEREN
bits of the HLT1CON1 register. External Resets do not
cause an HLTMR1 output event.
9.4 HLTimer1 Output
The unscaled output of HLTMR1 is available only to the
COG module, where it is used as a selectable limit to
the maximum COG period.
9.5 HLT Operation During Sleep
The HLT cannot be operated while the processor is in
Sleep mode. The contents of the HLTMR1 register will
remain unchanged while the processor is in Sleep
mode.
Note: HLTMR1 is not cleared when HLT1CON0 is
written.