Datasheet

 2011 Microchip Technology Inc. Preliminary DS41576B-page 23
PIC12F752/HV752
2.2.2.6 PIR1 Register
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-6.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
TMR1GIF ADIF
— — — HLTMR1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit
1 = Timer1 gate interrupt is pending
0 = Timer1 gate interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started
bit 5-3 Unimplemented: Read as ‘0’
bit 2 HLTMR1IF: Hardware Limit Timer1 to HLTPR1 Match Interrupt Flag bit
1 = HLTMR1 to HLTPR1 match occurred (must be cleared in software)
0 = HLTMR1 to HLTPR1 match did not occur
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur
bit 0 TMR1IF: Timer1 Interrupt Flag bit
1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 has not rolled over