Datasheet
2011 Microchip Technology Inc. Preliminary DS41576B-page 15
PIC12F752/HV752
TABLE 2-2: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR/BOR
Reset
Values on
all other
Resets
(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
81h OPTION_REG
RAPU
INTEDG T0CS T0SE PSA PS<2:0>
1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS
IRP RP1 RP0 TO
PD ZDCC
0001 1xxx 000q quuu
84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA — — TRISA5 TRISA4 TRISA3
(3)
TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
86h — Unimplemented — —
87h — Unimplemented — —
88h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
89h — Unimplemented — —
8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF
(2)
0000 0000 0000 0000
8Ch PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 00-- -000 00-- -000
8Dh PIE2 — — C2IE C1IE — COG1IE — CCP1IE --00 -0-0 --00 -0-0
8Eh — Unimplemented — —
8Fh OSCCON
— —
IRCF<1:0>
—
HTS LTS
—
--01 -00- --uu -uu-
90h FVRCON FVREN FVRRDY FVR-
BUFEN
FVR-
BUFSS
— — — —
0000 ---- 0000 ----
91h DACCON0 DACEN DACRNG DACOE — — DACPSS0 — — 000- -0-- 000- -0--
92h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000
93h
to
9Ah
— Unimplemented — —
9Bh CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100
9Ch CM2CON1 C2INTP C2INTN C2PCH<1:0> — — — C2NCH0 0000 ---0 0000 ---0
9Dh CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100
9Eh CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 0000 ---0 0000 ---0
9Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
2: MCLR
and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.
3: TRISA3 always reads ‘1’.