Datasheet
PIC12F752/HV752
DS41576B-page 14 Preliminary 2011 Microchip Technology Inc.
TABLE 2-1: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0
Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets
(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Holding register for the 8-bit TMR0 xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS
IRP RP1 RP0 TO
PD ZDCC
0001 1xxx 000q quuu
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA
— —
RA5 RA4 RA3 RA2 RA1 RA0
--xx xxxx --uu uuuu
06h
— Unimplemented — —
07h
— Unimplemented — —
08h IOCAF
— —
IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
--00 0000 --00 0000
09h
— Unimplemented — —
0Ah PCLATH
— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF
(2)
0000 0000 0000 0000
0Ch PIR1
TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 00---000 00---000
0Dh PIR2
— — C2IF C1IF — COG1IF — CCP1IF --00 -0-0 --00 -0-0
0Eh
— Unimplemented — —
0Fh
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx
uuuu uuuu
10h
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
11h
T1CON
TMR1CS<1:0> T1CKPS<1:0>
Reserved
T1SYNC
—
TMR1ON 0000 00-0
uuuu uu-u
12h T1GCON
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0>
0000 0x00 uuuu uxuu
13h
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu
14h
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu
15h
CCP1CON
— —
DC1B<1:0> CCP1M<3:0>
--00 0000 --00 0000
16h
to
1Bh
— Unimplemented — —
1Ch
ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx uuuu uuuu
1Dh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx uuuu uuuu
1Eh
ADCON0 ADFM VCFG CHS<3:0> GO/DONE
ADON
0000 0000 0000 0000
1Fh
ADCON1
— ADCS<2:0> — — — —
-000 ---- -000 ----
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
2: MCLR
and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.