Datasheet

PIC12F752/HV752
DS41576B-page 76 Preliminary  2011 Microchip Technology Inc.
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH HLT
REGISTER 9-2: HLT1CON1: HLT1 CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — H1ERS<2:0> H1FEREN H1REREN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 H1ERS<2:0>: Hardware Limit Timer 1 Peripheral Reset Select bits
000 = CCP1 Out
001 =C1OUT
010 =C2OUT
011 =COG1FLT
100 =COG1OUT0
101 =COG1OUT1
110 = Reserved - ‘0’ input
111 = Reserved - ‘0’ input
bit 1 H1FEREN: Hardware Limit Timer 1 Falling Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a falling edge of selected Reset source
0 = Falling edges of selected source have no effect
bit 0 H1REREN: Hardware Limit Timer 1 Rising Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a rising edge of selected Reset source
0 = Rising edges of selected source have no effect
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CCP1CON
— — DC1B<1:0> CCP1M<3:0> 83
CM1CON0 C1ON
C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 127
CM1CON1
C1INTP C1INTN C1PCH<1:0> — —
— C1NCH0
128
CM2CON0 C2ON
C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 127
CM2CON1
C2INTP C2INTN C2PCH<1:0> — —
— C2NCH0
128
INTCON GIE PEIE
T0IE INTE IOCIE T0IF INTF IOCIF 20
PIE1
TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21
PIR1
TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23
HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 73*
HLTPR1 HLTMR1 Module Period Register 73*
HLT1CON0
— H1OUTPS<3:0> H1ON H1CKPS<1:0> 75
HLT1CON1
— — — H1ERS<2:0> H1FEREN H1REREN
76
Legend: — = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation.
* Page provides register information.