Datasheet

 2011 Microchip Technology Inc. Preliminary DS41576B-page 73
PIC12F752/HV752
9.0 HARDWARE LIMIT TIMER (HLT)
MODULE
The Hardware Limit Timer (HLT) module is a version of
the Timer2-type modules. In addition to all the Timer2-
type features, the HLT can be reset on rising and falling
events from selected peripheral outputs.
The HLT primary purpose is to act as a timed hardware
limit to be used in conjunction with asynchronous
analog feedback applications. The external reset
source synchronizes the HLTMR1 to an analog
application.
In normal operation, the external reset source from the
analog application should occur before the HLTMR1
matches the HLTPR1. This resets HLTMR1 for the next
period and prevents the HLTimer1 Output from going
active.
When the external reset source fails to generate a
signal within the expected time, (allowing the HLTMR1
to match the HLTPR1), then the HLTimer1 Output
becomes active.
The HLT module incorporates the following features:
• 8-bit Read-Write Timer Register (HLTMR1)
• 8-bit Read-Write Period register (HLTPR1)
• Software programmable prescaler:
-1:1
-1:4
-1:16
• Software programmable postscaler
- 1:1 to 1:16, inclusive
• Interrupt on HLTMR1 match with HLTPR1
• 8 selectable timer Reset inputs (5 reserved)
• Reset on rising and falling event
Refer to Figure 9-1 for a block diagram of the HLT.
FIGURE 9-1: HLTMR1 BLOCK DIAGRAM
Comparator
HLTimer1 Output
Sets Flag bit HLTMR1IF
HLTMR1
Reset
Postscaler
Prescaler
HLTPR1
F
OSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
H1OUTPS<3:0>
H1CKPS<1:0>
Detect
H1FEREN
H1REREN
H1ERS<2:0>
Detect
CCP1 out
C1OUT
C2OUT
‘0’
‘0’
COG1OUT1
COG1OUT0
COG1FLT
000
111
H1ON
(to COG module)
3
2
4