Datasheet

PIC12F752/HV752
DS41576B-page 48 Preliminary  2011 Microchip Technology Inc.
5.4 PORTA Control Registers
REGISTER 5-2: PORTA: PORTA REGISTER
U-0 U-0 R/W-x/u R/W-x/u R-x/x R/W-x/u R/W-x/u R/W-x/u
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Value bits
(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
REGISTER 5-3: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 TRISA3
(1)
TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits
(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA3 always reads ‘1’.
REGISTER 5-4: LATA: PORTA DATA LATCH REGISTER
U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— —LATA5LATA4— LATA2 LATA1 LATA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 LATA<5:4>: PORTA Output Latch Value bits
(1)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LATA<2:0>: PORTA Output Latch Value bits
(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.