Datasheet

PIC12F752/HV752
DS41576B-page 22 Preliminary  2011 Microchip Technology Inc.
2.2.2.5 PIE2 Register
The PIE2 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-5.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
— — C2IE C1IE —COG1IE — CCP1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 4 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 COG1IE: COG 1 Interrupt Flag bit
1 = COG1 interrupt enabled
0 = COG1 interrupt disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt