Datasheet

 2011 Microchip Technology Inc. Preliminary DS41576B-page 183
PIC12F752/HV752
FIGURE 20-6: RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING
FIGURE 20-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset
(1)
Watchdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset
(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33*
37
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
Reset
(due to BOR)
VBOR + VHYST