Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 8 8-Bit 20 MHz I/O number 5

 2011 Microchip Technology Inc. Preliminary DS41576B-page 17

PIC12F752/HV752

TABLE 2-4: PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR/BOR

Reset

Values on

all other

Resets

(1)

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

181h OPTION_REG

RAPU

INTEDG T0CS T0SE PSA PS<2:0>

1111 1111 1111 1111

182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h STATUS

IRP RP1 RP0 TO

PD ZDCC

0001 1xxx 000q quuu

184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

185h ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 --11 -111 --11 -111

186h

— Unimplemented — —

187h

— Unimplemented — —

188h APFCON

— — —

T1GSEL

— COG1FSEL COG1O1SEL COG1O0SEL ---0 -000 ---0 -000

189h OSCTUNE — — — TUN<4:0> ---0 0000 ---u uuuu

18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

18Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

(2)

0000 0000 0000 0000

18Ch PMCON1 — — — — —WRENWR RD---- -000 ---- -000

18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----

18Eh PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000

18Fh PMADRH — — — — — — PMADRH<1:0> ---- --00 ---- --00

190h PMDATL Program Memory Data Register Low Byte 0000 0000 0000 0000

191h PMDATH — — Program Memory Data Register High Byte --00 0000 --00 0000

192h COG1PH

— — — —

G1PH<3:0> ---- xxxx ---- uuuu

193h COG1BLK G1BLKR<3:0> G1BLKF<3:0> xxxx xxxx uuuu uuuu

194h COG1DB G1DBR<3:0> G1DBF<3:0> xxxx xxxx uuuu uuuu

195h COG1CON0

G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS<1:0>

0000 0000 0000 0000

196h COG1CON1

G1FSIM G1RSIM

G1FS<2:0> G1RS<2:0>

0000 0000 0000 0000

197h COG1ASD

G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT

0000 0000 0000 0000

198h

19Fh

— Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

2: MCLR

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch exists.