Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 8 8-Bit 20 MHz I/O number 5

PIC12F752/HV752

DS41576B-page 16 Preliminary  2011 Microchip Technology Inc.

TABLE 2-3: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 2

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR/BOR

Reset

Value on

all other

Resets

(1)

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

101h TMR0 Holding Register for the 8-bit Timer0 Register xxxx xxxx uuuu uuuu

102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h STATUS

IRP RP1

RP0 TO PD ZDCC0001 1xxx 000q quuu

104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

105h LATA — —LATA5LATA4— LATA2 LATA1 LATA0 --xx -xxx --uu -uuu

106h — Unimplemented — —

107h — Unimplemented — —

108h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000

109h — Unimplemented — —

10Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

10Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF

(2)

0000 0000 0000 0000

10Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000

10Dh SLRCONA — — — — —SLRA2 —SLRA0---- -0-0 ---- -0-0

10Eh — Unimplemented — —

10Fh PCON — — — — — —PORBOR ---- --qq ---- --uu

110h

TMR2 Holding Register for the 8-bit Timer2 Register 0000 0000 0000 0000

111h PR2 Timer2 Period Register 1111 1111 1111 1111

112h T2CON — TOUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000

113h HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 0000 0000 0000 0000

114h HLTPR1 Hardware Limit Timer1 Period Register 1111 1111 1111 1111

115h HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> -000 0000 -000 0000

116h HLT1CON1 — — — H1ERS<2:0> H1FEREN H1REREN ---0 0000 ---0 0000

117h

11Fh

— Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

2: MCLR

and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the

mismatch exists.