Datasheet

PIC12F752/HV752
DS41576B-page 154 Preliminary  2011 Microchip Technology Inc.
FIGURE 17-8: INT PIN INTERRUPT TIMING
TABLE 17-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF
20
IOCAF
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 52
IOCAN
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 52
IOCAP
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 52
LATA
— —LATA5LATA4— LATA2 LATA1 LATA0 48
PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 21
PIR1
TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 23
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
CLKIN
CLKOUT
INT pin
INTF flag
(INTCON reg.)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC – 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in
Section 20.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(3)
(4)
(5)
(1)