Datasheet

PIC12F752/HV752
DS41576B-page 152 Preliminary  2011 Microchip Technology Inc.
17.4 Interrupts
The PIC12F752/HV752 has multiple sources of inter-
rupt:
• External Interrupt (INT pin)
• Interrupt-On-Change (IOC) Interrupts
• Timer0 Overflow Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Hardware Limit Timer (HLT) Interrupt
• Comparator Interrupt (C1/C2)
• ADC Interrupt
• Complementary Output Generator (COG)
• CCP1 Interrupt
• Flash Memory Self Write
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Registers (PIRx) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIEx registers. GIE is
cleared on Reset.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• Interrupt-On-Change (IOC) Interrupts
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the PIR1
and PIR2 registers. The corresponding interrupt enable
bit is contained in the PIE1 and PIE2 registers.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• Comparator Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Enhanced CCP Interrupt
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 17-8). The latency is the same for one or two-
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, Timer2,
comparators, ADC, Enhanced CCP modules, refer to
the respective peripheral section.
17.4.1 RA2/INT INTERRUPT
The external interrupt on the RA2/INT pin is edge-
triggered; either on the rising edge if the INTEDG bit of
the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
RA2/INT pin, the INTF bit of the INTCON register is set.
This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The RA2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 17.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 17-10 for timing of wake-up from Sleep through
RA2/INT interrupt.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’ and cannot generate an
interrupt.